60 lines
1.5 KiB
C
60 lines
1.5 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PLATFORM_DEF_H__
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#define __PLATFORM_DEF_H__
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#include <common_def.h>
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#include <tbbr/tbbr_img_def.h>
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#define PLATFORM_STACK_SIZE 0x1000
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << (CACHE_WRITEBACK_SHIFT))
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/* topology */
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#define UNIPHIER_MAX_CPUS_PER_CLUSTER 4
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#define UNIPHIER_CLUSTER_COUNT 2
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#define PLATFORM_CORE_COUNT \
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((UNIPHIER_MAX_CPUS_PER_CLUSTER) * (UNIPHIER_CLUSTER_COUNT))
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#define PLAT_MAX_PWR_LVL 1
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#define PLAT_MAX_OFF_STATE 2
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#define PLAT_MAX_RET_STATE 1
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#define UNIPHIER_SEC_DRAM_BASE 0x80000000
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#define UNIPHIER_SEC_DRAM_LIMIT 0x82000000
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#define UNIPHIER_SEC_DRAM_SIZE ((UNIPHIER_SEC_DRAM_LIMIT) - \
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(UNIPHIER_SEC_DRAM_BASE))
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#define BL2_BASE (UNIPHIER_SEC_DRAM_BASE)
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#define BL2_LIMIT ((BL2_BASE) + 0x00020000)
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#define BL31_BASE (BL2_LIMIT)
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#define BL31_LIMIT ((BL31_BASE) + 0x00080000)
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#define BL32_BASE (BL31_LIMIT)
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#define BL32_LIMIT (UNIPHIER_SEC_DRAM_LIMIT)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_XLAT_TABLES_DYNAMIC 1
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#define MAX_XLAT_TABLES 7
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#define MAX_MMAP_REGIONS 6
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#define MAX_IO_HANDLES 2
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#define MAX_IO_DEVICES 2
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#define MAX_IO_BLOCK_DEVICES 1
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#define TSP_SEC_MEM_BASE (BL32_BASE)
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#define TSP_SEC_MEM_SIZE ((BL32_LIMIT) - (BL32_BASE))
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#define TSP_IRQ_SEC_PHY_TIMER 29
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#endif /* __PLATFORM_DEF_H__ */
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