Caesar Wang 4ea8dc4e02 rockchip: fix A72 L2CTLR_DATA_RAM_LATENCY to 5 ... The default value of L2CTLR_DATA_RAM_LATENCY is 2, depends to the test result on rk3399, the A72 will need lower voltage for high frequency if it's set to be 5, and almost no effect on performance. Change-Id: I99a6a43edcc0c58f7775c10f4b85669dc3eff66d Signed-off-by: Caesar Wang <wxt@rock-chips.com>		2016-10-25 03:32:31 +08:00
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aarch64	rockchip: fix A72 L2CTLR_DATA_RAM_LATENCY to 5	2016-10-25 03:32:31 +08:00
drivers/pmu	rockchip: support the suspend/resume for rk3399	2016-07-18 19:58:06 +08:00
include	rockchip: set gpio2 ~ gpio4 to input and pull none mode	2016-09-10 04:06:44 +08:00
pmusram	rockchip: fix the power up/dowm cnt for rk3399	2016-08-11 13:12:10 +08:00
bl31_plat_setup.c	rockchip: add reset or power off gpio configuration for rk3399	2016-05-27 09:39:56 +08:00
params_setup.c	rockchip: set gpio2 ~ gpio4 to input and pull none mode	2016-09-10 04:06:44 +08:00
plat_pm.c	rockchip: fixes some typo	2016-09-10 06:37:23 +08:00
plat_topology.c	rockchip: support the suspend/resume for rk3399	2016-07-18 19:58:06 +08:00
rockchip_gicv2.c	Introduce utils.h header file	2016-07-08 14:37:11 +01:00
rockchip_gicv3.c	Introduce utils.h header file	2016-07-08 14:37:11 +01:00
rockchip_sip_svc.c	rockchip: support plat SIP runtime service	2016-07-18 19:45:03 +08:00