167 lines
3.8 KiB
C
167 lines
3.8 KiB
C
/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <common/debug.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/console.h>
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#include <errno.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include "aml_private.h"
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#define SCPI_POWER_ON 0
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#define SCPI_POWER_RETENTION 1
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#define SCPI_POWER_OFF 3
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#define SCPI_SYSTEM_SHUTDOWN 0
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#define SCPI_SYSTEM_REBOOT 1
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static uintptr_t axg_sec_entrypoint;
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static void axg_pm_set_reset_addr(u_register_t mpidr, uint64_t value)
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{
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unsigned int core = plat_calc_core_pos(mpidr);
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uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4);
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mmio_write_64(cpu_mailbox_addr, value);
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}
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static void axg_pm_reset(u_register_t mpidr, uint32_t value)
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{
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unsigned int core = plat_calc_core_pos(mpidr);
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uintptr_t cpu_mailbox_addr = AML_PSCI_MAILBOX_BASE + (core << 4) + 8;
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mmio_write_32(cpu_mailbox_addr, value);
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}
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static void __dead2 axg_system_reset(void)
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{
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u_register_t mpidr = read_mpidr_el1();
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int ret;
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INFO("BL31: PSCI_SYSTEM_RESET\n");
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ret = aml_scpi_sys_power_state(SCPI_SYSTEM_REBOOT);
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if (ret != 0) {
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ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %i\n", ret);
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panic();
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}
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axg_pm_reset(mpidr, 0);
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wfi();
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ERROR("BL31: PSCI_SYSTEM_RESET: Operation not handled\n");
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panic();
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}
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static void __dead2 axg_system_off(void)
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{
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u_register_t mpidr = read_mpidr_el1();
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int ret;
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INFO("BL31: PSCI_SYSTEM_OFF\n");
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ret = aml_scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
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if (ret != 0) {
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ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %i\n", ret);
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panic();
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}
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axg_pm_set_reset_addr(mpidr, 0);
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axg_pm_reset(mpidr, 0);
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dmbsy();
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wfi();
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ERROR("BL31: PSCI_SYSTEM_OFF: Operation not handled\n");
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panic();
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}
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static int32_t axg_pwr_domain_on(u_register_t mpidr)
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{
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axg_pm_set_reset_addr(mpidr, axg_sec_entrypoint);
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aml_scpi_set_css_power_state(mpidr,
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SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON);
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dmbsy();
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sev();
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return PSCI_E_SUCCESS;
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}
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static void axg_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
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PLAT_LOCAL_STATE_OFF);
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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axg_pm_set_reset_addr(read_mpidr_el1(), 0);
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}
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static void axg_pwr_domain_off(const psci_power_state_t *target_state)
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{
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u_register_t mpidr = read_mpidr_el1();
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uint32_t system_state = SCPI_POWER_ON;
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uint32_t cluster_state = SCPI_POWER_ON;
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assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
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PLAT_LOCAL_STATE_OFF);
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axg_pm_reset(mpidr, -1);
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gicv2_cpuif_disable();
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if (target_state->pwr_domain_state[MPIDR_AFFLVL2] ==
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PLAT_LOCAL_STATE_OFF)
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system_state = SCPI_POWER_OFF;
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if (target_state->pwr_domain_state[MPIDR_AFFLVL1] ==
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PLAT_LOCAL_STATE_OFF)
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cluster_state = SCPI_POWER_OFF;
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aml_scpi_set_css_power_state(mpidr,
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SCPI_POWER_OFF, cluster_state,
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system_state);
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}
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static void __dead2 axg_pwr_domain_pwr_down_wfi(const psci_power_state_t
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*target_state)
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{
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dsbsy();
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axg_pm_reset(read_mpidr_el1(), 0);
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for (;;)
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wfi();
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}
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/*******************************************************************************
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* Platform handlers and setup function.
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******************************************************************************/
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static const plat_psci_ops_t axg_ops = {
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.pwr_domain_on = axg_pwr_domain_on,
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.pwr_domain_on_finish = axg_pwr_domain_on_finish,
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.pwr_domain_off = axg_pwr_domain_off,
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.pwr_domain_pwr_down_wfi = axg_pwr_domain_pwr_down_wfi,
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.system_off = axg_system_off,
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.system_reset = axg_system_reset
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};
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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axg_sec_entrypoint = sec_entrypoint;
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*psci_ops = &axg_ops;
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return 0;
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}
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