Jeenu Viswambharan 48e1d350a0 AArch64: Use SSBS for CVE_2018_3639 mitigation ... The Armv8.5 extensions introduces PSTATE.SSBS (Speculation Store Bypass Safe) bit to mitigate against Variant 4 vulnerabilities. Although an Armv8.5 feature, this can be implemented by CPUs implementing earlier version of the architecture. With this patch, when both PSTATE.SSBS is implemented and DYNAMIC_WORKAROUND_CVE_2018_3639 is active, querying for SMCCC_ARCH_WORKAROUND_2 via. SMCCC_ARCH_FEATURES call would return 1 to indicate that mitigation on the PE is either permanently enabled or not required. When SSBS is implemented, SCTLR_EL3.DSSBS is initialized to 0 at reset of every BL stage. This means that EL3 always executes with mitigation applied. For Cortex A76, if the PE implements SSBS, the existing mitigation (by using a different vector table, and tweaking CPU ACTLR2) is not used. Change-Id: Ib0386c5714184144d4747951751c2fc6ba4242b6 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>		2018-12-10 14:28:58 +00:00
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aarch32	Make errata reporting mandatory for CPU files	2018-10-29 09:54:32 +00:00
aarch64	AArch64: Use SSBS for CVE_2018_3639 mitigation	2018-12-10 14:28:58 +00:00
cpu-ops.mk	DSU erratum 936184 workaround	2018-08-17 10:34:43 +01:00
errata_report.c	Fix MISRA defects in workaround and errata framework	2018-10-29 14:41:48 +00:00