PSCI requires a core to turn itself off, which we can't do properly by just executing an algorithm on that very core. As a consequence we just put a core into WFI on CPU_OFF right now. To fix this let's task the "arisc" management processor (an OpenRISC core) with that task of asserting reset and turning off the core's power domain. We use a handcrafted sequence of OpenRISC instructions to achieve this, and hand this data over to the new sunxi_execute_arisc_code() routine. The commented source code for this routine is provided in a separate file, but the ATF code contains the already encoded instructions as data. The H6 uses the same algorithm, but differs in the MMIO addresses, so provide a SoC (family) specific copy of that code. Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
||
---|---|---|
.. | ||
include | ||
allwinner-common.mk | ||
arisc_off.S | ||
plat_helpers.S | ||
sunxi_bl31_setup.c | ||
sunxi_common.c | ||
sunxi_cpu_ops.c | ||
sunxi_pm.c | ||
sunxi_security.c | ||
sunxi_topology.c |