Dimitris Papastamos f62ad32269 Workaround for CVE-2017-5715 on Cortex A57 and A72 ... Invalidate the Branch Target Buffer (BTB) on entry to EL3 by disabling and enabling the MMU. To achieve this without performing any branch instruction, a per-cpu vbar is installed which executes the workaround and then branches off to the corresponding vector entry in the main vector table. A side effect of this change is that the main vbar is configured before any reset handling. This is to allow the per-cpu reset function to override the vbar setting. This workaround is enabled by default on the affected CPUs. Change-Id: I97788d38463a5840a410e3cea85ed297a1678265 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>		2018-01-11 10:26:15 +00:00
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aem_generic.S	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
cortex_a35.S	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
cortex_a53.S	CPU: Correct names of implementation-defined aux regs	2017-08-29 13:52:48 +01:00
cortex_a55.S	Fix order of #includes	2017-07-12 14:45:31 +01:00
cortex_a57.S	Workaround for CVE-2017-5715 on Cortex A57 and A72	2018-01-11 10:26:15 +00:00
cortex_a72.S	Workaround for CVE-2017-5715 on Cortex A57 and A72	2018-01-11 10:26:15 +00:00
cortex_a73.S	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
cortex_a75.S	Implement support for the Activity Monitor Unit on Cortex A75	2017-11-29 09:36:05 +00:00
cpu_helpers.S	Use a callee-saved register to be AAPCS-compliant	2017-05-24 14:23:08 +01:00
denver.S	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
workaround_cve_2017_5715_mmu.S	Workaround for CVE-2017-5715 on Cortex A57 and A72	2018-01-11 10:26:15 +00:00