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Cortex X2 erratum 2058056 is a Cat B erratum present in the X2 core. It applies to revisions r0p0, r1p0, and r2p0 and is still open. There are 2 ways this workaround can be accomplished, the first of which involves executing a few additional instructions around MSR writes to CPUECTLR when disabling the prefetcher. (see SDEN for details) However, this patch implements the 2nd possible workaround which sets the prefetcher into its most conservative mode, since this workaround is generic. SDEN can be found here: https://developer.arm.com/documentation/SDEN1775100 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Idb20d9928c986616cd5bedf40bb29d46d384cfd3 |
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| .. | ||
| alt-boot-flows.rst | ||
| auth-framework.rst | ||
| cpu-specific-build-macros.rst | ||
| firmware-design.rst | ||
| index.rst | ||
| interrupt-framework-design.rst | ||
| psci-pd-tree.rst | ||
| reset-design.rst | ||
| trusted-board-boot-build.rst | ||
| trusted-board-boot.rst | ||