Manish Pandey f7a92518f6 Merge changes from topic "st_ddr_updates" into integration ... * changes: refactor(st-ddr): move basic tests in a dedicated file refactor(st-ddr): reorganize generic and specific elements feat(stm32mp1): allow configuration of DDR AXI ports number refactor(st-ddr): update parameter array initialization feat(st-ddr): add read valid training support refactor(stm32mp1): remove the support of calibration result fix(st-ddr): correct DDR warnings		2022-01-07 17:24:54 +01:00
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common	fix(st): manage UART clock and reset only in BL2	2022-01-05 18:54:59 +01:00
stm32mp1	refactor(st-ddr): move basic tests in a dedicated file	2022-01-05 11:47:46 +01:00