75 lines
1.8 KiB
C
75 lines
1.8 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <mmio.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <sunxi_def.h>
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#include <xlat_tables_v2.h>
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#include "sunxi_private.h"
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static mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = {
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MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE,
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MT_MEMORY | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE,
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MT_MEMORY | MT_RW | MT_SECURE),
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MAP_REGION(PLAT_SUNXI_NS_IMAGE_OFFSET,
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SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE,
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SUNXI_DRAM_MAP_SIZE,
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MT_MEMORY | MT_RO | MT_NS),
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{},
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};
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unsigned int plat_get_syscnt_freq2(void)
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{
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return SUNXI_OSC24M_CLK_IN_HZ;
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}
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uintptr_t plat_get_ns_image_entrypoint(void)
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{
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#ifdef PRELOADED_BL33_BASE
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return PRELOADED_BL33_BASE;
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#else
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return PLAT_SUNXI_NS_IMAGE_OFFSET;
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#endif
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}
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void sunxi_configure_mmu_el3(int flags)
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{
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mmap_add_region(BL31_BASE, BL31_BASE,
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BL31_LIMIT - BL31_BASE,
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MT_MEMORY | MT_RW | MT_SECURE);
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mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
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BL_CODE_END - BL_CODE_BASE,
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MT_CODE | MT_SECURE);
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mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE,
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BL_RO_DATA_END - BL_RO_DATA_BASE,
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MT_RO_DATA | MT_SECURE);
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mmap_add(sunxi_mmap);
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init_xlat_tables();
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enable_mmu_el3(0);
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}
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#define SRAM_VER_REG (SUNXI_SYSCON_BASE + 0x24)
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uint16_t sunxi_read_soc_id(void)
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{
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uint32_t reg = mmio_read_32(SRAM_VER_REG);
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/* Set bit 15 to prepare for the SOCID read. */
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mmio_write_32(SRAM_VER_REG, reg | BIT(15));
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reg = mmio_read_32(SRAM_VER_REG);
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/* deactivate the SOCID access again */
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mmio_write_32(SRAM_VER_REG, reg & ~BIT(15));
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return reg >> 16;
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}
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