262 lines
8.5 KiB
C
262 lines
8.5 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <debug.h>
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#include <platform.h>
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#include <xlat_tables.h>
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/*******************************************************************************
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* This array holds the characteristics of the differences between the three
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* FVP platforms (Base, A53_A57 & Foundation). It will be populated during cold
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* boot at each boot stage by the primary before enabling the MMU (to allow cci
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* configuration) & used thereafter. Each BL will have its own copy to allow
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* independent operation.
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******************************************************************************/
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static unsigned long platform_config[CONFIG_LIMIT];
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/*******************************************************************************
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* Enable the MMU assuming that the pagetables have already been created
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*******************************************************************************/
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void enable_mmu()
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{
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unsigned long mair, tcr, ttbr, sctlr;
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unsigned long current_el = read_current_el();
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/* Set the attributes in the right indices of the MAIR */
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mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);
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mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR,
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ATTR_IWBWA_OWBWA_NTR_INDEX);
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/*
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* Set TCR bits as well. Inner & outer WBWA & shareable + T0SZ = 32
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*/
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tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA |
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TCR_RGN_INNER_WBA | TCR_T0SZ_4GB;
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/* Set TTBR bits as well */
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ttbr = (unsigned long) l1_xlation_table;
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if (GET_EL(current_el) == MODE_EL3) {
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write_mair_el3(mair);
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tcr |= TCR_EL3_RES1;
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/* Invalidate EL3 TLBs */
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tlbialle3();
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write_tcr_el3(tcr);
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write_ttbr0_el3(ttbr);
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sctlr = read_sctlr_el3();
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sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT | SCTLR_I_BIT;
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sctlr |= SCTLR_A_BIT | SCTLR_C_BIT;
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write_sctlr_el3(sctlr);
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} else {
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write_mair_el1(mair);
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/* Invalidate EL1 TLBs */
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tlbivmalle1();
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write_tcr_el1(tcr);
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write_ttbr0_el1(ttbr);
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sctlr = read_sctlr_el1();
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sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT | SCTLR_I_BIT;
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sctlr |= SCTLR_A_BIT | SCTLR_C_BIT;
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write_sctlr_el1(sctlr);
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}
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return;
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}
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void disable_mmu(void)
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{
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unsigned long sctlr;
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unsigned long current_el = read_current_el();
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if (GET_EL(current_el) == MODE_EL3) {
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sctlr = read_sctlr_el3();
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sctlr = sctlr & ~(SCTLR_M_BIT | SCTLR_C_BIT);
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write_sctlr_el3(sctlr);
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} else {
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sctlr = read_sctlr_el1();
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sctlr = sctlr & ~(SCTLR_M_BIT | SCTLR_C_BIT);
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write_sctlr_el1(sctlr);
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}
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/* Flush the caches */
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dcsw_op_all(DCCISW);
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return;
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}
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/*
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* Table of regions to map using the MMU.
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* This doesn't include TZRAM as the 'mem_layout' argument passed to to
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* configure_mmu() will give the available subset of that,
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*/
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const mmap_region_t fvp_mmap[] = {
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{ TZROM_BASE, TZROM_SIZE, MT_MEMORY | MT_RO | MT_SECURE },
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{ TZDRAM_BASE, TZDRAM_SIZE, MT_MEMORY | MT_RW | MT_SECURE },
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{ FLASH0_BASE, FLASH0_SIZE, MT_MEMORY | MT_RO | MT_SECURE },
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{ FLASH1_BASE, FLASH1_SIZE, MT_MEMORY | MT_RO | MT_SECURE },
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{ VRAM_BASE, VRAM_SIZE, MT_MEMORY | MT_RW | MT_SECURE },
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{ DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
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{ NSRAM_BASE, NSRAM_SIZE, MT_MEMORY | MT_RW | MT_NS },
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{ DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
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/* 2nd GB as device for now...*/
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{ 0x40000000, 0x40000000, MT_DEVICE | MT_RW | MT_SECURE },
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{ DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS },
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{0}
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};
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/*******************************************************************************
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* Setup the pagetables as per the platform memory map & initialize the mmu
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*******************************************************************************/
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void configure_mmu(meminfo_t *mem_layout,
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unsigned long ro_start,
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unsigned long ro_limit,
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unsigned long coh_start,
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unsigned long coh_limit)
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{
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mmap_add_region(mem_layout->total_base, mem_layout->total_size,
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MT_MEMORY | MT_RW | MT_SECURE);
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mmap_add_region(ro_start, ro_limit - ro_start,
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MT_MEMORY | MT_RO | MT_SECURE);
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mmap_add_region(coh_start, coh_limit - coh_start,
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MT_DEVICE | MT_RW | MT_SECURE);
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mmap_add(fvp_mmap);
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init_xlat_tables();
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enable_mmu();
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return;
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}
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/* Simple routine which returns a configuration variable value */
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unsigned long platform_get_cfgvar(unsigned int var_id)
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{
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assert(var_id < CONFIG_LIMIT);
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return platform_config[var_id];
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}
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/*******************************************************************************
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* A single boot loader stack is expected to work on both the Foundation FVP
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* models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
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* SYS_ID register provides a mechanism for detecting the differences between
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* these platforms. This information is stored in a per-BL array to allow the
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* code to take the correct path.Per BL platform configuration.
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******************************************************************************/
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int platform_config_setup(void)
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{
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unsigned int rev, hbi, bld, arch, sys_id, midr_pn;
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sys_id = mmio_read_32(VE_SYSREGS_BASE + V2M_SYS_ID);
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rev = (sys_id >> SYS_ID_REV_SHIFT) & SYS_ID_REV_MASK;
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hbi = (sys_id >> SYS_ID_HBI_SHIFT) & SYS_ID_HBI_MASK;
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bld = (sys_id >> SYS_ID_BLD_SHIFT) & SYS_ID_BLD_MASK;
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arch = (sys_id >> SYS_ID_ARCH_SHIFT) & SYS_ID_ARCH_MASK;
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if ((rev != REV_FVP) || (arch != ARCH_MODEL))
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panic();
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/*
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* The build field in the SYS_ID tells which variant of the GIC
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* memory is implemented by the model.
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*/
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switch (bld) {
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case BLD_GIC_VE_MMAP:
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platform_config[CONFIG_GICD_ADDR] = VE_GICD_BASE;
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platform_config[CONFIG_GICC_ADDR] = VE_GICC_BASE;
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platform_config[CONFIG_GICH_ADDR] = VE_GICH_BASE;
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platform_config[CONFIG_GICV_ADDR] = VE_GICV_BASE;
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break;
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case BLD_GIC_A53A57_MMAP:
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platform_config[CONFIG_GICD_ADDR] = BASE_GICD_BASE;
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platform_config[CONFIG_GICC_ADDR] = BASE_GICC_BASE;
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platform_config[CONFIG_GICH_ADDR] = BASE_GICH_BASE;
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platform_config[CONFIG_GICV_ADDR] = BASE_GICV_BASE;
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break;
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default:
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assert(0);
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}
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/*
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* The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010
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* for the Foundation FVP.
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*/
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switch (hbi) {
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case HBI_FOUNDATION:
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platform_config[CONFIG_MAX_AFF0] = 4;
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platform_config[CONFIG_MAX_AFF1] = 1;
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platform_config[CONFIG_CPU_SETUP] = 0;
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platform_config[CONFIG_BASE_MMAP] = 0;
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platform_config[CONFIG_HAS_CCI] = 0;
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platform_config[CONFIG_HAS_TZC] = 0;
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break;
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case HBI_FVP_BASE:
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midr_pn = (read_midr() >> MIDR_PN_SHIFT) & MIDR_PN_MASK;
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if ((midr_pn == MIDR_PN_A57) || (midr_pn == MIDR_PN_A53))
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platform_config[CONFIG_CPU_SETUP] = 1;
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else
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platform_config[CONFIG_CPU_SETUP] = 0;
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platform_config[CONFIG_MAX_AFF0] = 4;
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platform_config[CONFIG_MAX_AFF1] = 2;
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platform_config[CONFIG_BASE_MMAP] = 1;
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platform_config[CONFIG_HAS_CCI] = 1;
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platform_config[CONFIG_HAS_TZC] = 1;
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break;
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default:
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assert(0);
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}
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return 0;
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}
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unsigned long plat_get_ns_image_entrypoint(void)
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{
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return NS_IMAGE_OFFSET;
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}
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uint64_t plat_get_syscnt_freq(void)
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{
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uint64_t counter_base_frequency;
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/* Read the frequency from Frequency modes table */
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counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF);
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/* The first entry of the frequency modes table must not be 0 */
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assert(counter_base_frequency != 0);
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return counter_base_frequency;
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}
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