360 lines
12 KiB
C
360 lines
12 KiB
C
/*
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* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <common/debug.h>
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#include "../qos_common.h"
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#include "qos_init_h3_v10.h"
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#define RCAR_QOS_VERSION "rev.0.36"
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#define RCAR_QOS_NONE (3U)
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#define RCAR_QOS_TYPE_DEFAULT (0U)
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#define RCAR_DRAM_SPLIT_LINEAR (0U)
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#define RCAR_DRAM_SPLIT_4CH (1U)
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#define RCAR_DRAM_SPLIT_2CH (2U)
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#define RCAR_DRAM_SPLIT_AUTO (3U)
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#define AXI_BASE (0xE6784000U)
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#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U)
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#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU)
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#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U)
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#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U)
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#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U)
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#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U)
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#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U)
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#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U)
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#define ADSPLCR0_SWP (0x0CU)
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#define MSTAT_BASE (0xE67E0000U)
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#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U)
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#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U)
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#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U)
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#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U)
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#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U)
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#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U)
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#define MSTAT_STATQC (MSTAT_BASE + 0x8008U)
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#define RALLOC_BASE (0xE67F0000U)
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#define RALLOC_RAS (RALLOC_BASE + 0x0000U)
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#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U)
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#define RALLOC_RAEN (RALLOC_BASE + 0x0018U)
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#define RALLOC_REGGD (RALLOC_BASE + 0x0020U)
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#define RALLOC_DANN (RALLOC_BASE + 0x0030U)
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#define RALLOC_DANT (RALLOC_BASE + 0x0038U)
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#define RALLOC_EC (RALLOC_BASE + 0x003CU)
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#define RALLOC_EMS (RALLOC_BASE + 0x0040U)
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#define RALLOC_INSFC (RALLOC_BASE + 0x0050U)
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#define RALLOC_BERR (RALLOC_BASE + 0x0054U)
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#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
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static const mstat_slot_t mstat_fix[] = {
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{0x0000U, 0x0000000000000000UL},
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{0x0008U, 0x0000000000000000UL},
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{0x0010U, 0x0000000000000000UL},
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{0x0018U, 0x0000000000000000UL},
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{0x0020U, 0x0000000000000000UL},
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{0x0028U, 0x0000000000000000UL},
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{0x0030U, 0x0000000000000000UL},
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{0x0038U, 0x0000000000000000UL},
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{0x0040U, 0x00140C050000FFFFUL},
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{0x0048U, 0x0000000000000000UL},
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{0x0050U, 0x0000000000000000UL},
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{0x0058U, 0x001404030000FFFFUL},
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{0x0060U, 0x001408060000FFFFUL},
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{0x0068U, 0x0000000000000000UL},
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{0x0070U, 0x0000000000000000UL},
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{0x0078U, 0x0000000000000000UL},
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{0x0080U, 0x0000000000000000UL},
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{0x0088U, 0x00140C050000FFFFUL},
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{0x0090U, 0x001408060000FFFFUL},
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{0x0098U, 0x001404020000FFFFUL},
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{0x00A0U, 0x0000000000000000UL},
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{0x00A8U, 0x0000000000000000UL},
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{0x00B0U, 0x0000000000000000UL},
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{0x00B8U, 0x0000000000000000UL},
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{0x00C0U, 0x0000000000000000UL},
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{0x00C8U, 0x0000000000000000UL},
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{0x00D0U, 0x0000000000000000UL},
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{0x00D8U, 0x0000000000000000UL},
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{0x00E0U, 0x0000000000000000UL},
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{0x00E8U, 0x0000000000000000UL},
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{0x00F0U, 0x0000000000000000UL},
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{0x00F8U, 0x0000000000000000UL},
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{0x0100U, 0x0000000000000000UL},
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{0x0108U, 0x0000000000000000UL},
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{0x0110U, 0x0000000000000000UL},
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{0x0118U, 0x0000000000000000UL},
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{0x0120U, 0x0000000000000000UL},
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{0x0128U, 0x0000000000000000UL},
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{0x0130U, 0x0000000000000000UL},
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{0x0138U, 0x001004020000FFFFUL},
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{0x0140U, 0x001004020000FFFFUL},
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{0x0148U, 0x001004020000FFFFUL},
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{0x0150U, 0x001008050000FFFFUL},
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{0x0158U, 0x001008050000FFFFUL},
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{0x0160U, 0x001008050000FFFFUL},
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{0x0168U, 0x001008050000FFFFUL},
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{0x0170U, 0x001008050000FFFFUL},
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{0x0178U, 0x001004030000FFFFUL},
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{0x0180U, 0x001004030000FFFFUL},
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{0x0188U, 0x001004030000FFFFUL},
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{0x0190U, 0x001014140000FFFFUL},
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{0x0198U, 0x001014140000FFFFUL},
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{0x01A0U, 0x001008060000FFFFUL},
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{0x01A8U, 0x001008060000FFFFUL},
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{0x01B0U, 0x001008060000FFFFUL},
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{0x01B8U, 0x0000000000000000UL},
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{0x01C0U, 0x0000000000000000UL},
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{0x01C8U, 0x0000000000000000UL},
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{0x01D0U, 0x0000000000000000UL},
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{0x01D8U, 0x0000000000000000UL},
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{0x01E0U, 0x0000000000000000UL},
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{0x01E8U, 0x0000000000000000UL},
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{0x01F0U, 0x0000000000000000UL},
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{0x01F8U, 0x0000000000000000UL},
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{0x0200U, 0x0000000000000000UL},
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{0x0208U, 0x0000000000000000UL},
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{0x0210U, 0x0000000000000000UL},
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{0x0218U, 0x0000000000000000UL},
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{0x0220U, 0x0000000000000000UL},
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{0x0228U, 0x0000000000000000UL},
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{0x0230U, 0x0000000000000000UL},
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{0x0238U, 0x0000000000000000UL},
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{0x0240U, 0x0000000000000000UL},
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{0x0248U, 0x0000000000000000UL},
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{0x0250U, 0x0000000000000000UL},
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{0x0258U, 0x0000000000000000UL},
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{0x0260U, 0x0000000000000000UL},
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{0x0268U, 0x0000000000000000UL},
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{0x0270U, 0x0000000000000000UL},
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{0x0278U, 0x0000000000000000UL},
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{0x0280U, 0x0000000000000000UL},
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{0x0288U, 0x0000000000000000UL},
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{0x0290U, 0x0000000000000000UL},
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{0x0298U, 0x0000000000000000UL},
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{0x02A0U, 0x0000000000000000UL},
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{0x02A8U, 0x0000000000000000UL},
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{0x02B0U, 0x0000000000000000UL},
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{0x02B8U, 0x0000000000000000UL},
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{0x02C0U, 0x0000000000000000UL},
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{0x02C8U, 0x0000000000000000UL},
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{0x02D0U, 0x0000000000000000UL},
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{0x02D8U, 0x0000000000000000UL},
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{0x02E0U, 0x0000000000000000UL},
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{0x02E8U, 0x0000000000000000UL},
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{0x02F0U, 0x0000000000000000UL},
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{0x02F8U, 0x0000000000000000UL},
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{0x0300U, 0x0000000000000000UL},
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{0x0308U, 0x0000000000000000UL},
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{0x0310U, 0x0000000000000000UL},
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{0x0318U, 0x0000000000000000UL},
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{0x0320U, 0x0000000000000000UL},
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{0x0328U, 0x0000000000000000UL},
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{0x0330U, 0x0000000000000000UL},
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{0x0338U, 0x0000000000000000UL},
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};
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static const mstat_slot_t mstat_be[] = {
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{0x0000U, 0x001000100C8FFC01UL},
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{0x0008U, 0x001000100C8FFC01UL},
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{0x0010U, 0x001000100C8FFC01UL},
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{0x0018U, 0x001000100C8FFC01UL},
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{0x0020U, 0x001000100C8FFC01UL},
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{0x0028U, 0x001000100C8FFC01UL},
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{0x0030U, 0x001000100C8FFC01UL},
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{0x0038U, 0x001000100C8FFC01UL},
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{0x0040U, 0x0000000000000000UL},
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{0x0048U, 0x0000000000000000UL},
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{0x0050U, 0x001000100C8FFC01UL},
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{0x0058U, 0x0000000000000000UL},
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{0x0060U, 0x0000000000000000UL},
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{0x0068U, 0x001000100C8FFC01UL},
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{0x0070U, 0x001000100C8FFC01UL},
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{0x0078U, 0x001000100C8FFC01UL},
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{0x0080U, 0x001000100C8FFC01UL},
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{0x0088U, 0x0000000000000000UL},
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{0x0090U, 0x0000000000000000UL},
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{0x0098U, 0x0000000000000000UL},
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{0x00A0U, 0x001000100C8FFC01UL},
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{0x00A8U, 0x001000100C8FFC01UL},
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{0x00B0U, 0x001000100C8FFC01UL},
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{0x00B8U, 0x001000100C8FFC01UL},
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{0x00C0U, 0x001000100C8FFC01UL},
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{0x00C8U, 0x001000100C8FFC01UL},
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{0x00D0U, 0x001000100C8FFC01UL},
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{0x00D8U, 0x002000200C8FFC01UL},
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{0x00E0U, 0x002000200C8FFC01UL},
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{0x00E8U, 0x001000100C8FFC01UL},
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{0x00F0U, 0x001000100C8FFC01UL},
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{0x00F8U, 0x001000100C8FFC01UL},
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{0x0100U, 0x0000000000000000UL},
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{0x0108U, 0x002000200C8FFC01UL},
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{0x0110U, 0x001000100C8FFC01UL},
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{0x0118U, 0x001000100C8FFC01UL},
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{0x0120U, 0x0000000000000000UL},
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{0x0128U, 0x002000200C8FFC01UL},
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{0x0130U, 0x001000100C8FFC01UL},
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{0x0138U, 0x0000000000000000UL},
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{0x0140U, 0x0000000000000000UL},
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{0x0148U, 0x0000000000000000UL},
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{0x0150U, 0x0000000000000000UL},
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{0x0158U, 0x0000000000000000UL},
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{0x0160U, 0x0000000000000000UL},
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{0x0168U, 0x0000000000000000UL},
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{0x0170U, 0x0000000000000000UL},
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{0x0178U, 0x0000000000000000UL},
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{0x0180U, 0x0000000000000000UL},
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{0x0188U, 0x0000000000000000UL},
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{0x0190U, 0x0000000000000000UL},
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{0x0198U, 0x0000000000000000UL},
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{0x01A0U, 0x0000000000000000UL},
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{0x01A8U, 0x0000000000000000UL},
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{0x01B0U, 0x0000000000000000UL},
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{0x01B8U, 0x001000100C8FFC01UL},
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{0x01C0U, 0x001000200C8FFC01UL},
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{0x01C8U, 0x001000200C8FFC01UL},
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{0x01D0U, 0x001000200C8FFC01UL},
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{0x01D8U, 0x001000200C8FFC01UL},
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{0x01E0U, 0x001000100C8FFC01UL},
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{0x01E8U, 0x001000100C8FFC01UL},
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{0x01F0U, 0x001000100C8FFC01UL},
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{0x01F8U, 0x001000100C8FFC01UL},
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{0x0200U, 0x001000100C8FFC01UL},
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{0x0208U, 0x001000100C8FFC01UL},
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{0x0210U, 0x001000100C8FFC01UL},
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{0x0218U, 0x001000100C8FFC01UL},
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{0x0220U, 0x001000100C8FFC01UL},
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{0x0228U, 0x001000100C8FFC01UL},
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{0x0230U, 0x001000100C8FFC01UL},
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{0x0238U, 0x001000100C8FFC01UL},
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{0x0240U, 0x001000100C8FFC01UL},
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{0x0248U, 0x001000100C8FFC01UL},
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{0x0250U, 0x001000100C8FFC01UL},
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{0x0258U, 0x001000100C8FFC01UL},
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{0x0260U, 0x001000100C8FFC01UL},
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{0x0268U, 0x001000100C8FFC01UL},
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{0x0270U, 0x001000100C8FFC01UL},
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{0x0278U, 0x001000100C8FFC01UL},
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{0x0280U, 0x001000100C8FFC01UL},
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{0x0288U, 0x001000100C8FFC01UL},
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{0x0290U, 0x001000100C8FFC01UL},
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{0x0298U, 0x001000100C8FFC01UL},
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{0x02A0U, 0x001000100C8FFC01UL},
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{0x02A8U, 0x001000100C8FFC01UL},
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{0x02B0U, 0x001000100C8FFC01UL},
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{0x02B8U, 0x001000100C8FFC01UL},
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{0x02C0U, 0x001000100C8FFC01UL},
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{0x02C8U, 0x001000100C8FFC01UL},
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{0x02D0U, 0x001000100C8FFC01UL},
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{0x02D8U, 0x001000100C8FFC01UL},
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{0x02E0U, 0x001000100C8FFC01UL},
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{0x02E8U, 0x001000100C8FFC01UL},
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{0x02F0U, 0x001000200C8FFC01UL},
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{0x02F8U, 0x001000300C8FFC01UL},
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{0x0300U, 0x0000000000000000UL},
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{0x0308U, 0x001000200C8FFC01UL},
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{0x0310U, 0x001000300C8FFC01UL},
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{0x0318U, 0x0000000000000000UL},
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{0x0320U, 0x001000200C8FFC01UL},
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{0x0328U, 0x001000300C8FFC01UL},
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{0x0330U, 0x001000200C8FFC01UL},
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{0x0338U, 0x001000300C8FFC01UL},
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};
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#endif
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void qos_init_h3_v10(void)
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{
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/* DRAM Split Address mapping */
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#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
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(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
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NOTICE("BL2: DRAM Split is 4ch\n");
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io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
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| ADSPLCR0_SPLITSEL(0xFFU)
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| ADSPLCR0_AREA(0x1BU)
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| ADSPLCR0_SWP);
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io_write_32(AXI_ADSPLCR1, 0x00000000U);
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io_write_32(AXI_ADSPLCR2, 0xA8A90000U);
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io_write_32(AXI_ADSPLCR3, 0x00000000U);
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#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
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NOTICE("BL2: DRAM Split is 2ch\n");
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io_write_32(AXI_ADSPLCR0, 0x00000000U);
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io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
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| ADSPLCR0_SPLITSEL(0xFFU)
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| ADSPLCR0_AREA(0x1BU)
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| ADSPLCR0_SWP);
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io_write_32(AXI_ADSPLCR2, 0x00000000U);
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io_write_32(AXI_ADSPLCR3, 0x00000000U);
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#else
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NOTICE("BL2: DRAM Split is OFF\n");
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#endif
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#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
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#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
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NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
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#endif
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/* AR Cache setting */
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io_write_32(0xE67D1000U, 0x00000100U);
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io_write_32(0xE67D1008U, 0x00000100U);
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/* Resource Alloc setting */
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io_write_32(RALLOC_RAS, 0x00000040U);
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io_write_32(RALLOC_FIXTH, 0x000F0005U);
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io_write_32(RALLOC_REGGD, 0x00000004U);
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io_write_64(RALLOC_DANN, 0x0202000004040404UL);
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io_write_32(RALLOC_DANT, 0x003C1110U);
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io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 v1.* */
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io_write_64(RALLOC_EMS, 0x0000000000000000UL);
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io_write_32(RALLOC_INSFC, 0xC7840001U);
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io_write_32(RALLOC_BERR, 0x00000000U);
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/* MSTAT setting */
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io_write_32(MSTAT_SL_INIT,
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SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
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io_write_32(MSTAT_REF_ARS, 0x00330000U);
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/* MSTAT SRAM setting */
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for (uint32_t i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
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io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
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mstat_fix[i].value);
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io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
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mstat_fix[i].value);
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}
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for (uint32_t i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
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io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
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mstat_be[i].value);
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io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
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mstat_be[i].value);
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}
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/* 3DG bus Leaf setting */
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io_write_32(0xFD820808U, 0x00001234U);
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io_write_32(0xFD820800U, 0x0000003FU);
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io_write_32(0xFD821800U, 0x0000003FU);
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io_write_32(0xFD822800U, 0x0000003FU);
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io_write_32(0xFD823800U, 0x0000003FU);
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io_write_32(0xFD824800U, 0x0000003FU);
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io_write_32(0xFD825800U, 0x0000003FU);
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io_write_32(0xFD826800U, 0x0000003FU);
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io_write_32(0xFD827800U, 0x0000003FU);
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/* Resource Alloc start */
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io_write_32(RALLOC_RAEN, 0x00000001U);
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/* MSTAT start */
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io_write_32(MSTAT_STATQC, 0x00000001U);
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#else
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NOTICE("BL2: QoS is None\n");
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/* Resource Alloc setting */
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io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 v1.* */
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#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
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}
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