Soby Mathew fdfabec10c Optimize EL3 register state stored in cpu_context structure ... This patch further optimizes the EL3 register state stored in cpu_context. The 2 registers which are removed from cpu_context are: * cntfrq_el0 is the system timer register which is writable only in EL3 and it can be programmed during cold/warm boot. Hence it need not be saved to cpu_context. * cptr_el3 controls access to Trace, Floating-point, and Advanced SIMD functionality and it is programmed every time during cold and warm boot. The current BL3-1 implementation does not need to modify the access controls during normal execution and hence they are expected to remain static. Fixes ARM-software/tf-issues#197 Change-Id: I599ceee3b73a7dcfd37069fd41b60e3d397a7b18		2014-07-31 10:09:58 +01:00
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aarch64	Optimize EL3 register state stored in cpu_context structure	2014-07-31 10:09:58 +01:00
bl31.ld.S	fvp: Reuse BL1 and BL2 memory through image overlaying	2014-07-10 16:34:54 +01:00
bl31.mk	Remove coherent stack usage from the warm boot path	2014-07-19 23:31:53 +01:00
bl31_main.c	Rework incorrect use of assert() and panic() in codebase	2014-07-28 12:20:16 +01:00
context_mgmt.c	Optimize EL3 register state stored in cpu_context structure	2014-07-31 10:09:58 +01:00
cpu_data_array.c	Rework the crash reporting in BL3-1 to use less stack	2014-07-28 11:03:20 +01:00
interrupt_mgmt.c	Rework incorrect use of assert() and panic() in codebase	2014-07-28 12:20:16 +01:00
runtime_svc.c	Remove all checkpatch errors from codebase	2014-06-24 12:50:00 +01:00