284 lines
10 KiB
C
284 lines
10 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <gic_v2.h>
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#include <interrupt_mgmt.h>
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#include <platform.h>
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#include "juno_def.h"
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#include "juno_private.h"
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/* Value used to initialise Non-Secure irq priorities four at a time */
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#define DEFAULT_NS_PRIORITY_X4 \
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(GIC_HIGHEST_NS_PRIORITY | \
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(GIC_HIGHEST_NS_PRIORITY << 8) | \
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(GIC_HIGHEST_NS_PRIORITY << 16) | \
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(GIC_HIGHEST_NS_PRIORITY << 24))
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/*******************************************************************************
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* Enable secure interrupts and use FIQs to route them. Disable legacy bypass
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* and set the priority mask register to allow all interrupts to trickle in.
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******************************************************************************/
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void gic_cpuif_setup(unsigned int gicc_base)
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{
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unsigned int val;
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gicc_write_pmr(gicc_base, GIC_PRI_MASK);
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val = ENABLE_GRP0 | FIQ_EN;
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val |= FIQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP0;
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val |= FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
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gicc_write_ctlr(gicc_base, val);
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}
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/*******************************************************************************
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* Place the cpu interface in a state where it can never make a cpu exit wfi as
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* as result of an asserted interrupt. This is critical for powering down a cpu
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******************************************************************************/
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void gic_cpuif_deactivate(unsigned int gicc_base)
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{
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unsigned int val;
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/* Disable secure, non-secure interrupts and disable their bypass */
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val = gicc_read_ctlr(gicc_base);
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val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
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val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
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val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
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gicc_write_ctlr(gicc_base, val);
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}
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static void gic_set_secure(unsigned int gicd_base, unsigned id)
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{
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/* Set interrupt as Group 0 */
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gicd_clr_igroupr(gicd_base, id);
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/* Set priority to max */
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gicd_set_ipriorityr(gicd_base, id, GIC_HIGHEST_SEC_PRIORITY);
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}
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/*******************************************************************************
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* Per cpu gic distributor setup which will be done by all cpus after a cold
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* boot/hotplug. This marks out the secure interrupts & enables them.
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******************************************************************************/
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void gic_pcpu_distif_setup(unsigned int gicd_base)
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{
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unsigned i;
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/* Mark all 32 PPI interrupts as Group 1 (non-secure) */
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mmio_write_32(gicd_base + GICD_IGROUPR, 0xffffffffu);
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/* Setup PPI priorities doing four at a time */
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for (i = 0; i < 32; i += 4)
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mmio_write_32(gicd_base + GICD_IPRIORITYR + i, DEFAULT_NS_PRIORITY_X4);
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/* Configure those PPIs we want as secure, and enable them. */
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static const char sec_irq[] = {
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IRQ_SEC_PHY_TIMER,
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IRQ_SEC_SGI_0,
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IRQ_SEC_SGI_1,
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IRQ_SEC_SGI_2,
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IRQ_SEC_SGI_3,
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IRQ_SEC_SGI_4,
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IRQ_SEC_SGI_5,
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IRQ_SEC_SGI_6,
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IRQ_SEC_SGI_7
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};
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for (i = 0; i < sizeof(sec_irq) / sizeof(sec_irq[0]); i++) {
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gic_set_secure(gicd_base, sec_irq[i]);
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gicd_set_isenabler(gicd_base, sec_irq[i]);
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}
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}
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/*******************************************************************************
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* Global gic distributor setup which will be done by the primary cpu after a
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* cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
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* then enables the secure GIC distributor interface.
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******************************************************************************/
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static void gic_distif_setup(unsigned int gicd_base)
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{
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unsigned int i, ctlr;
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const unsigned int ITLinesNumber =
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gicd_read_typer(gicd_base) & IT_LINES_NO_MASK;
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/* Disable the distributor before going further */
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ctlr = gicd_read_ctlr(gicd_base);
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ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1);
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gicd_write_ctlr(gicd_base, ctlr);
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/* Mark all lines of SPIs as Group 1 (non-secure) */
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for (i = 0; i < ITLinesNumber; i++)
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mmio_write_32(gicd_base + GICD_IGROUPR + 4 + i * 4, 0xffffffffu);
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/* Setup SPI priorities doing four at a time */
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for (i = 0; i < ITLinesNumber * 32; i += 4)
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mmio_write_32(gicd_base + GICD_IPRIORITYR + 32 + i, DEFAULT_NS_PRIORITY_X4);
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/* Configure the SPIs we want as secure */
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static const char sec_irq[] = {
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IRQ_MHU,
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IRQ_GPU_SMMU_0,
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IRQ_GPU_SMMU_1,
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IRQ_ETR_SMMU,
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IRQ_TZC400,
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IRQ_TZ_WDOG
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};
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for (i = 0; i < sizeof(sec_irq) / sizeof(sec_irq[0]); i++)
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gic_set_secure(gicd_base, sec_irq[i]);
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/* Route watchdog interrupt to this CPU and enable it. */
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gicd_set_itargetsr(gicd_base, IRQ_TZ_WDOG,
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platform_get_core_pos(read_mpidr()));
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gicd_set_isenabler(gicd_base, IRQ_TZ_WDOG);
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/* Now setup the PPIs */
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gic_pcpu_distif_setup(gicd_base);
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/* Enable Group 0 (secure) interrupts */
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gicd_write_ctlr(gicd_base, ctlr | ENABLE_GRP0);
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}
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void gic_setup(void)
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{
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gic_cpuif_setup(GICC_BASE);
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gic_distif_setup(GICD_BASE);
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}
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/*******************************************************************************
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* An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
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* The interrupt controller knows which pin/line it uses to signal a type of
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* interrupt. The platform knows which interrupt controller type is being used
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* in a particular security state e.g. with an ARM GIC, normal world could use
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* the GICv2 features while the secure world could use GICv3 features and vice
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* versa.
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* This function is exported by the platform to let the interrupt management
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* framework determine for a type of interrupt and security state, which line
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* should be used in the SCR_EL3 to control its routing to EL3. The interrupt
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* line is represented as the bit position of the IRQ or FIQ bit in the SCR_EL3.
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******************************************************************************/
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uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
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{
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assert(type == INTR_TYPE_S_EL1 ||
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type == INTR_TYPE_EL3 ||
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type == INTR_TYPE_NS);
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assert(sec_state_is_valid(security_state));
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/*
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* We ignore the security state parameter because Juno is GICv2 only
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* so both normal and secure worlds are using ARM GICv2.
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*/
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return gicv2_interrupt_type_to_line(GICC_BASE, type);
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}
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/*******************************************************************************
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* This function returns the type of the highest priority pending interrupt at
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* the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
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* interrupt pending.
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******************************************************************************/
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uint32_t plat_ic_get_pending_interrupt_type(void)
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{
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uint32_t id;
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id = gicc_read_hppir(GICC_BASE);
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/* Assume that all secure interrupts are S-EL1 interrupts */
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if (id < 1022)
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return INTR_TYPE_S_EL1;
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if (id == GIC_SPURIOUS_INTERRUPT)
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return INTR_TYPE_INVAL;
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return INTR_TYPE_NS;
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}
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/*******************************************************************************
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* This function returns the id of the highest priority pending interrupt at
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* the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no
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* interrupt pending.
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******************************************************************************/
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uint32_t plat_ic_get_pending_interrupt_id(void)
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{
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uint32_t id;
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id = gicc_read_hppir(GICC_BASE);
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if (id < 1022)
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return id;
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if (id == 1023)
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return INTR_ID_UNAVAILABLE;
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/*
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* Find out which non-secure interrupt it is under the assumption that
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* the GICC_CTLR.AckCtl bit is 0.
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*/
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return gicc_read_ahppir(GICC_BASE);
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}
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/*******************************************************************************
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* This functions reads the GIC cpu interface Interrupt Acknowledge register
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* to start handling the pending interrupt. It returns the contents of the IAR.
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******************************************************************************/
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uint32_t plat_ic_acknowledge_interrupt(void)
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{
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return gicc_read_IAR(GICC_BASE);
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}
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/*******************************************************************************
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* This functions writes the GIC cpu interface End Of Interrupt register with
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* the passed value to finish handling the active interrupt
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******************************************************************************/
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void plat_ic_end_of_interrupt(uint32_t id)
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{
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gicc_write_EOIR(GICC_BASE, id);
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}
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/*******************************************************************************
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* This function returns the type of the interrupt id depending upon the group
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* this interrupt has been configured under by the interrupt controller i.e.
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* group0 or group1.
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******************************************************************************/
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uint32_t plat_ic_get_interrupt_type(uint32_t id)
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{
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uint32_t group;
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group = gicd_get_igroupr(GICD_BASE, id);
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/* Assume that all secure interrupts are S-EL1 interrupts */
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if (group == GRP0)
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return INTR_TYPE_S_EL1;
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else
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return INTR_TYPE_NS;
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}
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