164 lines
7.2 KiB
C
164 lines
7.2 KiB
C
/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __TEGRA_DEF_H__
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#define __TEGRA_DEF_H__
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/*******************************************************************************
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* These values are used by the PSCI implementation during the `CPU_SUSPEND`
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* and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
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* parameter.
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******************************************************************************/
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#define PSTATE_ID_CORE_IDLE 6
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#define PSTATE_ID_CORE_POWERDN 7
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#define PSTATE_ID_SOC_POWERDN 2
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/*******************************************************************************
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* Platform power states (used by PSCI framework)
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*
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* - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
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* - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
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******************************************************************************/
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#define PLAT_MAX_RET_STATE 1
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#define PLAT_MAX_OFF_STATE 8
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/*******************************************************************************
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* Implementation defined ACTLR_EL3 bit definitions
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******************************************************************************/
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#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
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#define ACTLR_EL3_L2ECTLR_BIT (1 << 5)
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#define ACTLR_EL3_L2CTLR_BIT (1 << 4)
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#define ACTLR_EL3_CPUECTLR_BIT (1 << 1)
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#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
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#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \
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ACTLR_EL3_L2ECTLR_BIT | \
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ACTLR_EL3_L2CTLR_BIT | \
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ACTLR_EL3_CPUECTLR_BIT | \
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ACTLR_EL3_CPUACTLR_BIT)
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/*******************************************************************************
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* Secure IRQ definitions
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******************************************************************************/
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#define TEGRA186_TOP_WDT_IRQ 49
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#define TEGRA186_AON_WDT_IRQ 50
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#define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */
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/*******************************************************************************
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* Tegra Miscellanous register constants
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******************************************************************************/
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#define TEGRA_MISC_BASE 0x00100000
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#define HARDWARE_REVISION_OFFSET 0x4
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#define MAJOR_VERSION_SHIFT 0x4
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#define MAJOR_VERSION_MASK 0xF
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#define MINOR_VERSION_SHIFT 0x10
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#define MINOR_VERSION_MASK 0xF
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#define MISCREG_PFCFG 0x200C
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/*******************************************************************************
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* Tegra TSA Controller constants
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******************************************************************************/
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#define TEGRA_TSA_BASE 0x02400000
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/*******************************************************************************
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* Tegra Memory Controller constants
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******************************************************************************/
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#define TEGRA_MC_STREAMID_BASE 0x02C00000
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#define TEGRA_MC_BASE 0x02C10000
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/*******************************************************************************
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* Tegra UART Controller constants
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******************************************************************************/
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#define TEGRA_UARTA_BASE 0x03100000
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#define TEGRA_UARTB_BASE 0x03110000
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#define TEGRA_UARTC_BASE 0x0C280000
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#define TEGRA_UARTD_BASE 0x03130000
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#define TEGRA_UARTE_BASE 0x03140000
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#define TEGRA_UARTF_BASE 0x03150000
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#define TEGRA_UARTG_BASE 0x0C290000
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/*******************************************************************************
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* GICv2 & interrupt handling related constants
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******************************************************************************/
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#define TEGRA_GICD_BASE 0x03881000
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#define TEGRA_GICC_BASE 0x03882000
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/*******************************************************************************
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* Security Engine related constants
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******************************************************************************/
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#define TEGRA_SE0_BASE 0x03AC0000
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#define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C
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#define TEGRA_PKA1_BASE 0x03AD0000
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#define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144
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#define TEGRA_RNG1_BASE 0x03AE0000
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#define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0
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/*******************************************************************************
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* Tegra Clock and Reset Controller constants
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******************************************************************************/
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#define TEGRA_CAR_RESET_BASE 0x05000000
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/*******************************************************************************
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* Tegra micro-seconds timer constants
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******************************************************************************/
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#define TEGRA_TMRUS_BASE 0x0C2E0000
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/*******************************************************************************
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* Tegra Power Mgmt Controller constants
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******************************************************************************/
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#define TEGRA_PMC_BASE 0x0C360000
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/*******************************************************************************
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* Tegra scratch registers constants
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******************************************************************************/
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#define TEGRA_SCRATCH_BASE 0x0C390000
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#define SECURE_SCRATCH_RSV6 0x680
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#define SECURE_SCRATCH_RSV11_LO 0x6A8
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#define SECURE_SCRATCH_RSV11_HI 0x6AC
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/*******************************************************************************
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* Tegra Memory Mapped Control Register Access Bus constants
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******************************************************************************/
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#define TEGRA_MMCRAB_BASE 0x0E000000
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/*******************************************************************************
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* Tegra SMMU Controller constants
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******************************************************************************/
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#define TEGRA_SMMU_BASE 0x12000000
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/*******************************************************************************
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* Tegra TZRAM constants
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******************************************************************************/
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#define TEGRA_TZRAM_BASE 0x30000000
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#define TEGRA_TZRAM_SIZE 0x50000
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#endif /* __TEGRA_DEF_H__ */
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