162 lines
6.3 KiB
C
162 lines
6.3 KiB
C
/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PLATFORM_DEF_H__
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#define __PLATFORM_DEF_H__
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#include <arch.h>
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/*******************************************************************************
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* Platform binary types for linking
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******************************************************************************/
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stacks */
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#define PLATFORM_STACK_SIZE 0x800
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/* Size of coherent stacks for debug and release builds */
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#if DEBUG
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#define PCPU_DV_MEM_STACK_SIZE 0x400
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#else
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#define PCPU_DV_MEM_STACK_SIZE 0x300
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#endif
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#define FIRMWARE_WELCOME_STR "Booting trusted firmware boot loader stage 1\n\r"
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/* Trusted Boot Firmware BL2 */
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#define BL2_IMAGE_NAME "bl2.bin"
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/* EL3 Runtime Firmware BL31 */
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#define BL31_IMAGE_NAME "bl31.bin"
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/* Secure Payload BL32 (Trusted OS) */
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#define BL32_IMAGE_NAME "bl32.bin"
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/* Non-Trusted Firmware BL33 and its load address */
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#define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */
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#define NS_IMAGE_OFFSET (DRAM1_BASE + 0x8000000) /* DRAM + 128MB */
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#define PLATFORM_CACHE_LINE_SIZE 64
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#define PLATFORM_CLUSTER_COUNT 2ull
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#define PLATFORM_CLUSTER0_CORE_COUNT 4
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#define PLATFORM_CLUSTER1_CORE_COUNT 4
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
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PLATFORM_CLUSTER0_CORE_COUNT)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
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#define PRIMARY_CPU 0x0
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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/*******************************************************************************
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* Platform memory map related constants
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******************************************************************************/
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#define TZROM_BASE 0x00000000
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#define TZROM_SIZE 0x04000000
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#define TZRAM_BASE 0x04000000
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#define TZRAM_SIZE 0x40000
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/* Location of trusted dram on the base fvp */
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#define TZDRAM_BASE 0x06000000
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#define TZDRAM_SIZE 0x02000000
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/*******************************************************************************
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* BL2 specific defines.
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******************************************************************************/
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#define BL2_BASE (TZRAM_BASE + TZRAM_SIZE - 0xc000)
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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#define BL31_BASE (TZRAM_BASE + 0x6000)
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/*******************************************************************************
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* BL32 specific defines.
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******************************************************************************/
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/*
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* On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
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*/
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#define TSP_IN_TZRAM 0
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#define TSP_IN_TZDRAM 1
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#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM
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# define TSP_SEC_MEM_BASE TZRAM_BASE
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# define TSP_SEC_MEM_SIZE TZRAM_SIZE
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# define BL32_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1c000)
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# define BL32_LIMIT BL2_BASE
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#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
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# define TSP_SEC_MEM_BASE TZDRAM_BASE
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# define TSP_SEC_MEM_SIZE TZDRAM_SIZE
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# define BL32_BASE (TZDRAM_BASE + 0x2000)
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# define BL32_LIMIT (TZDRAM_BASE + (1 << 21))
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#else
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# error "Unsupported TSP_RAM_LOCATION_ID value"
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#endif
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define ADDR_SPACE_SIZE (1ull << 32)
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#define MAX_XLAT_TABLES 3
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#define MAX_MMAP_REGIONS 16
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/*******************************************************************************
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* CCI-400 related constants
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******************************************************************************/
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#define CCI400_BASE 0x2c090000
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#define CCI400_SL_IFACE_CLUSTER0 3
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#define CCI400_SL_IFACE_CLUSTER1 4
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#define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \
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CCI400_SL_IFACE_CLUSTER1 : \
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CCI400_SL_IFACE_CLUSTER0)
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/*******************************************************************************
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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* to the platform as it might have a combination of integrated and external
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* caches. Such alignment ensures that two maiboxes do not sit on the same cache
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* line at any cache level. They could belong to different cpus/clusters &
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* get written while being protected by different locks causing corruption of
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* a valid mailbox address.
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******************************************************************************/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#endif /* __PLATFORM_DEF_H__ */
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