Juan Castillo eb57fa5685 Improvements to ARM GIC driver ... This patch introduces several improvements to the ARM GIC driver: * In function gicd_set_itargetsr(), target CPU is specified using the same bit mask detailed in the GICD_ITARGETSRn register instead of the CPU linear ID, removing the dependency between bit position and linear ID in the platform porting. The current CPU bit mask may be obtained by reading GICD_ITARGETSR0. * PPIs and SGIs are initialized in arm_gic_pcpu_distif_setup(). SPIs are initialized in arm_gic_distif_setup(). * By default, non secure interrupts are assigned the maximum priority allowed to a non secure interrupt (defined by GIC_HIGHEST_NS_PRIORITY). * GICR base address is allowed to be NULL for GICv1 and GICv2. Change-Id: Ie2837fe860d43b2282e582dfdb13c39c6186f232		2014-10-31 18:40:23 +00:00
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arm_gic.c	Improvements to ARM GIC driver	2014-10-31 18:40:23 +00:00
gic_v2.c	Improvements to ARM GIC driver	2014-10-31 18:40:23 +00:00
gic_v3.c	Reduce deep nesting of header files	2014-05-06 13:57:48 +01:00