68 lines
2.3 KiB
ArmAsm
68 lines
2.3 KiB
ArmAsm
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <platform_def.h>
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.globl clst_warmboot_data
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#define PLL_MODE_SHIFT (0x8)
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#define PLL_NORMAL_MODE ((0x3 << (PLL_MODE_SHIFT + 16)) | \
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(0x1 << PLL_MODE_SHIFT))
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#define MPIDR_CLST_L_BITS 0x0
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/*
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* For different socs, if we want to speed up warmboot,
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* we need to config some regs here.
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* If scu was suspend, we must resume related clk
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* from slow (24M) mode to normal mode first.
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* X0: MPIDR_EL1 & MPIDR_CLUSTER_MASK
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*/
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.macro func_rockchip_clst_warmboot
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adr x4, clst_warmboot_data
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lsr x5, x0, #6
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ldr w3, [x4, x5]
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str wzr, [x4, x5]
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cmp w3, #PMU_CLST_RET
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b.ne clst_warmboot_end
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ldr w6, =(PLL_NORMAL_MODE)
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/*
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* core_l offset is CRU_BASE + 0xc,
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* core_b offset is CRU_BASE + 0x2c
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*/
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ldr x7, =(CRU_BASE + 0xc)
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lsr x2, x0, #3
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str w6, [x7, x2]
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clst_warmboot_end:
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.endm
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.macro rockchip_clst_warmboot_data
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clst_warmboot_data:
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.rept PLATFORM_CLUSTER_COUNT
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.word 0
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.endr
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.endm
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