86 lines
2.6 KiB
C
86 lines
2.6 KiB
C
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <mmio.h>
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#include <plat_sip_calls.h>
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#include <rockchip_sip_svc.h>
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#include <runtime_svc.h>
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#include <dram.h>
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#define RK_SIP_DDR_CFG 0x82000008
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#define DRAM_INIT 0x00
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#define DRAM_SET_RATE 0x01
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#define DRAM_ROUND_RATE 0x02
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#define DRAM_SET_AT_SR 0x03
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#define DRAM_GET_BW 0x04
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#define DRAM_GET_RATE 0x05
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#define DRAM_CLR_IRQ 0x06
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#define DRAM_SET_PARAM 0x07
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uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, uint64_t id)
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{
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switch (id) {
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case DRAM_INIT:
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ddr_init();
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break;
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case DRAM_SET_RATE:
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return ddr_set_rate((uint32_t)arg0);
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case DRAM_ROUND_RATE:
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return ddr_round_rate((uint32_t)arg0);
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case DRAM_GET_RATE:
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return ddr_get_rate();
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case DRAM_CLR_IRQ:
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clr_dcf_irq();
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break;
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case DRAM_SET_PARAM:
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dts_timing_receive((uint32_t)arg0, (uint32_t)arg1);
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break;
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default:
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break;
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}
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return 0;
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}
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uint64_t rockchip_plat_sip_handler(uint32_t smc_fid,
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uint64_t x1,
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uint64_t x2,
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uint64_t x3,
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uint64_t x4,
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void *cookie,
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void *handle,
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uint64_t flags)
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{
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switch (smc_fid) {
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case RK_SIP_DDR_CFG:
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SMC_RET1(handle, ddr_smc_handler(x1, x2, x3));
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default:
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ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
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SMC_RET1(handle, SMC_UNK);
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}
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}
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