156 lines
5.1 KiB
C
156 lines
5.1 KiB
C
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <cassert.h>
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#include <platform_def.h>
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#include <utils.h>
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#include <xlat_tables.h>
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#include "../xlat_tables_private.h"
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/*
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* Each platform can define the size of the virtual address space, which is
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* defined in ADDR_SPACE_SIZE. TTBCR.TxSZ is calculated as 32 minus the width
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* of said address space. The value of TTBCR.TxSZ must be in the range 0 to
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* 7 [1], which means that the virtual address space width must be in the range
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* 32 to 25 bits.
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*
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* Here we calculate the initial lookup level from the value of ADDR_SPACE_SIZE.
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* For a 4 KB page size, level 1 supports virtual address spaces of widths 32
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* to 31 bits, and level 2 from 30 to 25. Wider or narrower address spaces are
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* not supported. As a result, level 3 cannot be used as initial lookup level
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* with 4 KB granularity [1].
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*
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* For example, for a 31-bit address space (i.e. ADDR_SPACE_SIZE == 1 << 31),
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* TTBCR.TxSZ will be programmed to (32 - 31) = 1. According to Table G4-5 in
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* the ARM ARM, the initial lookup level for such an address space is 1.
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*
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* See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more
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* information:
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* [1] Section G4.6.5
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*/
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#if ADDR_SPACE_SIZE > (1ULL << (32 - TTBCR_TxSZ_MIN))
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# error "ADDR_SPACE_SIZE is too big."
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#elif ADDR_SPACE_SIZE > (1 << L1_XLAT_ADDRESS_SHIFT)
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# define XLAT_TABLE_LEVEL_BASE 1
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# define NUM_BASE_LEVEL_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT)
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#elif ADDR_SPACE_SIZE >= (1 << (32 - TTBCR_TxSZ_MAX))
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# define XLAT_TABLE_LEVEL_BASE 2
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# define NUM_BASE_LEVEL_ENTRIES (ADDR_SPACE_SIZE >> L2_XLAT_ADDRESS_SHIFT)
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#else
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# error "ADDR_SPACE_SIZE is too small."
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#endif
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static uint64_t base_xlation_table[NUM_BASE_LEVEL_ENTRIES]
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__aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
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void init_xlat_tables(void)
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{
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unsigned long long max_pa;
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uintptr_t max_va;
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print_mmap();
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init_xlation_table(0, base_xlation_table, XLAT_TABLE_LEVEL_BASE,
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&max_va, &max_pa);
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assert(max_va < ADDR_SPACE_SIZE);
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}
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/*******************************************************************************
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* Function for enabling the MMU in Secure PL1, assuming that the
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* page-tables have already been created.
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******************************************************************************/
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void enable_mmu_secure(unsigned int flags)
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{
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unsigned int mair0, ttbcr, sctlr;
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uint64_t ttbr0;
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assert(IS_IN_SECURE());
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assert((read_sctlr() & SCTLR_M_BIT) == 0);
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/* Set attributes in the right indices of the MAIR */
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mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);
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mair0 |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR,
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ATTR_IWBWA_OWBWA_NTR_INDEX);
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mair0 |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE,
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ATTR_NON_CACHEABLE_INDEX);
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write_mair0(mair0);
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/* Invalidate TLBs at the current exception level */
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tlbiall();
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/*
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* Set TTBCR bits as well. Set TTBR0 table properties as Inner
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* & outer WBWA & shareable. Disable TTBR1.
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*/
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ttbcr = TTBCR_EAE_BIT |
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TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA |
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TTBCR_RGN0_INNER_WBA |
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(32 - __builtin_ctzl((uintptr_t)ADDR_SPACE_SIZE));
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ttbcr |= TTBCR_EPD1_BIT;
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write_ttbcr(ttbcr);
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/* Set TTBR0 bits as well */
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ttbr0 = (uintptr_t) base_xlation_table;
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write64_ttbr0(ttbr0);
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write64_ttbr1(0);
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/*
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* Ensure all translation table writes have drained
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* into memory, the TLB invalidation is complete,
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* and translation register writes are committed
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* before enabling the MMU
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*/
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dsb();
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isb();
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sctlr = read_sctlr();
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sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT;
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if (flags & DISABLE_DCACHE)
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sctlr &= ~SCTLR_C_BIT;
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else
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sctlr |= SCTLR_C_BIT;
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write_sctlr(sctlr);
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/* Ensure the MMU enable takes effect immediately */
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isb();
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}
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