86 lines
3.3 KiB
C
86 lines
3.3 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEMCTRL_H__
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#define __MEMCTRL_H__
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#include <mmio.h>
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#include <tegra_def.h>
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/* SMMU registers */
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#define MC_SMMU_CONFIG_0 0x10
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#define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0
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#define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1
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#define MC_SMMU_TLB_CONFIG_0 0x14
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#define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010
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#define MC_SMMU_PTC_CONFIG_0 0x18
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#define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003f
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#define MC_SMMU_TLB_FLUSH_0 0x30
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#define TLB_FLUSH_VA_MATCH_ALL 0
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#define TLB_FLUSH_ASID_MATCH_DISABLE 0
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#define TLB_FLUSH_ASID_MATCH_SHIFT 31
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#define MC_SMMU_TLB_FLUSH_ALL \
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(TLB_FLUSH_VA_MATCH_ALL | \
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(TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT))
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#define MC_SMMU_PTC_FLUSH_0 0x34
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#define MC_SMMU_PTC_FLUSH_ALL 0
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#define MC_SMMU_ASID_SECURITY_0 0x38
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#define MC_SMMU_ASID_SECURITY 0
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#define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228
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#define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22c
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#define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230
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#define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234
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#define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98
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#define MC_SMMU_TRANSLATION_ENABLE (~0)
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/* TZDRAM carveout configuration registers */
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#define MC_SECURITY_CFG0_0 0x70
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#define MC_SECURITY_CFG1_0 0x74
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/* Video Memory carveout configuration registers */
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#define MC_VIDEO_PROTECT_BASE 0x648
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#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
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static inline uint32_t tegra_mc_read_32(uint32_t off)
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{
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return mmio_read_32(TEGRA_MC_BASE + off);
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}
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static inline void tegra_mc_write_32(uint32_t off, uint32_t val)
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{
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mmio_write_32(TEGRA_MC_BASE + off, val);
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}
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void tegra_memctrl_setup(void);
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void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes);
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void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes);
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#endif /* __MEMCTRL_H__ */
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