live-bootstrap/sysa/musl-1.1.24/patches/fenv.patch

64 lines
1.2 KiB
Diff

SPDX-FileCopyrightText: 2021 Andrius Štikonas <andrius@stikonas.eu>
SPDX-FileCopyrightText: 2021 fosslinux <fosslinux@aussies.space>
SPDX-License-Identifier: MIT
tcc does not seem to support stmxcsr and ldmxcsr.
Remove those. This might break float exception handling but we
are unlikely to need it.
diff -U3 -r src/fenv/i386/fenv.s src/fenv/i386/fenv.s
--- src/fenv/i386/fenv.s 2019-10-13 22:58:27.000000000 +0100
+++ src/fenv/i386/fenv.s 2021-02-01 00:27:04.924135707 +0000
@@ -17,7 +17,6 @@
jz 1f
fnclex
1: push %edx
- stmxcsr (%esp)
pop %edx
and $0x3f,%eax
or %eax,%edx
@@ -26,7 +25,6 @@
not %ecx
and %ecx,%edx
push %edx
- ldmxcsr (%esp)
pop %edx
1: xor %eax,%eax
ret
@@ -77,11 +75,9 @@
pop %edx
testl $0x02000000,(%edx)
jz 1f
- stmxcsr (%esp)
shl $3,%ch
andb $0x9f,1(%esp)
or %ch,1(%esp)
- ldmxcsr (%esp)
1: pop %ecx
ret
@@ -107,7 +103,6 @@
testl $0x02000000,(%edx)
jz 1f
push %eax
- stmxcsr (%esp)
pop %edx
and $0x3f,%edx
or %edx,4(%ecx)
@@ -143,7 +138,6 @@
shl $3,%ecx
or $0x1f80,%ecx
mov %ecx,4(%esp)
- ldmxcsr 4(%esp)
1: ret
.global fetestexcept
@@ -158,7 +152,6 @@
pop %edx
testl $0x02000000,(%edx)
jz 1f
- stmxcsr 4(%esp)
or 4(%esp),%eax
1: and %ecx,%eax
ret