Commit Graph

3 Commits

Author SHA1 Message Date
Ekaitz c0c2556c2b mescc: Add support for signed rotation.
* module/mescc/compile.scm (expr->register)[rshift, assn-expr]: Add
signed right-rotation support.
* lib/arm-mes/arm.M1 (asr): Add instruction.
* lib/x86-mes/x86.M1 (sar): Add instruction.
* lib/x86_64-mes/x86_64.M1 (sar): Add instruction.
* module/mescc/armv4/as.scm (r0>>r1-signed): Add variable.
* module/mescc/i386/as.scm (r0>>r1-signed): Add variable.
* module/mescc/riscv64/as.scm (r0>>r1-signed): Add variable.
* module/mescc/x86_64/as.scm (r0>>r1-signed): Add variable.
2023-09-11 17:20:45 +02:00
Andrius Štikonas 01991aff74 riscv64: Port to word based mescc-tools.
* module/mescc/M1.scm (riscv:i-format, riscv:j-format, riscv:u-format):
New procedures for RISC-V instruction formats.
(info->M1): Use them to switch from !0xAB to M1
weird strings 'AB'.
* module/mescc/riscv64/as.scm,
lib/linux/riscv64-mes-m2/_exit.c
ib/linux/riscv64-mes-m2/_write.c,.
lib/linux/riscv64-mes-m2/crt1.M1,.
lib/linux/riscv64-mes-m2/syscall.c,.
lib/linux/riscv64-mes-mescc/_exit.c,.
lib/linux/riscv64-mes-mescc/_write.c,.
lib/linux/riscv64-mes-mescc/crt1.c,.
lib/linux/riscv64-mes-mescc/syscall-internal.c,.
lib/linux/riscv64-mes-mescc/syscall.c,.
lib/m2/riscv64/riscv64_defs.M1,.
lib/riscv64-mes-mescc/setjmp.c,.
lib/riscv64-mes/riscv64.M1: Switch to riscv64 word-based macros.
* lib/linux/open.c (open)[!SYS_open]: Add support using openat syscall.
* include/linux/riscv64/syscall.h (MAKESTRING, MAKESTRING2,
RISCV_SYSCALL): New macros.
2023-07-17 09:06:32 +02:00
W. J. van der Laan 760f7bc891 mescc: RISC-V64 code generation.
* mes/module/mescc/mescc.mes: Import riscv64 code generation modules.
* mes/module/mescc/riscv64/as.mes: Imports for as.mes.
* mes/module/mescc/riscv64/info.mes: Imports for info.mes.
* module/mescc/mescc.scm (replace-suffix, arch-get, arch-get-info,
arch-get-machine, arch-get-m1-macros, .E?, .s?, .o?): Handle riscv64 and
some stubs for riscv32.
(arch-get-defines): Add defines for riscv32 and riscv64.
* module/mescc/riscv64/as.scm: New file: Code generator module for RISC-V64.
* module/mescc/riscv64/info.scm: New file: Architecture info for RISC-V64.
* build-aux/build-guile.sh (SCM_FILES): Add them.
2023-07-17 09:06:32 +02:00