## Copyright (C) 2021 Andrius Štikonas ## This file is part of M2-Planet. ## ## M2-Planet is free software: you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation, either version 3 of the License, or ## (at your option) any later version. ## ## M2-Planet is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License ## along with M2-Planet. If not, see . DEFINE NULL 0000000000000000 ;; Opcodes ;; RV32I Base Instruction Set DEFINE LUI 37000000 DEFINE AUIPC 17000000 DEFINE JAL 6F000000 DEFINE JALR 67000000 DEFINE BEQ 63000000 DEFINE BNE 63100000 DEFINE BLT 63400000 DEFINE BGE 63500000 DEFINE BLTU 63600000 DEFINE BGEU 63700000 DEFINE LB 03000000 DEFINE LH 03100000 DEFINE LW 03200000 DEFINE LBU 03400000 DEFINE LHU 03500000 DEFINE SB 23000000 DEFINE SH 23100000 DEFINE SW 23200000 DEFINE ADDI 13000000 DEFINE SLTI 13200000 DEFINE SLTIU 13300000 DEFINE XORI 13400000 DEFINE ORI 13600000 DEFINE ANDI 13700000 DEFINE SLLI 13100000 DEFINE SRLI 13500000 DEFINE SRAI 13500040 DEFINE ADD 33000000 DEFINE SUB 33000040 DEFINE SLL 33100000 DEFINE SLT 33200000 DEFINE SLTU 33300000 DEFINE XOR 33400000 DEFINE SRL 33500000 DEFINE SRA 33500040 DEFINE OR 33600000 DEFINE AND 33700000 DEFINE ECALL 73000000 ;; RV64I Base Instruction set DEFINE LWU 03600000 DEFINE LD 03300000 DEFINE SD 23300000 DEFINE ADDIW 1B000000 DEFINE SLLIW 1B100000 DEFINE SRLIW 1B500000 DEFINE SRAIW 1B500040 DEFINE ADDW 3B000000 DEFINE SUBW 3B000040 DEFINE SLLW 3B100000 DEFINE SRLW 3B500000 DEFINE SRAW 3B500040 ;; RV32M Standard Extensions DEFINE MUL 33000002 DEFINE MULH 33100002 DEFINE MULHSU 33200002 DEFINE MULHU 33300002 DEFINE DIV 33400002 DEFINE DIVU 33500002 DEFINE REM 33600002 DEFINE REMU 33700002 ;; RV64M Standard Extensions DEFINE MULW 3B000002 DEFINE DIVW 3B400002 DEFINE DIVUW 3B500002 DEFINE REMW 3B600002 DEFINE REMUW 3B700002 ;; Pseudoinstructions DEFINE NOP 13000000 # ADDI DEFINE MV 13000000 # ADDI DEFINE NOT 1340F0FF # XORI, RD, RS, -1 DEFINE BEQZ 63000000 # BEQ DEFINE BNEZ 63100000 # BNE DEFINE BLTZ 63400000 # BLT DEFINE RETURN 67800000 # RS1_RA JALR ;; Destination registers ;; register_number << 7 DEFINE RD_RA .80000000 DEFINE RD_SP .00010000 DEFINE RD_GP .80010000 DEFINE RD_TP .00020000 DEFINE RD_T0 .80020000 DEFINE RD_T1 .00030000 DEFINE RD_T2 .80030000 DEFINE RD_S0 .00040000 DEFINE RD_FP .00040000 DEFINE RD_S1 .80040000 DEFINE RD_A0 .00050000 DEFINE RD_A1 .80050000 DEFINE RD_A2 .00060000 DEFINE RD_A3 .80060000 DEFINE RD_A4 .00070000 DEFINE RD_A5 .80070000 DEFINE RD_A6 .00080000 DEFINE RD_A7 .80080000 DEFINE RD_S2 .00090000 DEFINE RD_S3 .80090000 DEFINE RD_S4 .000A0000 DEFINE RD_S5 .800A0000 DEFINE RD_S6 .000B0000 DEFINE RD_S7 .800B0000 DEFINE RD_S8 .000C0000 DEFINE RD_S9 .800C0000 DEFINE RD_S10 .000D0000 DEFINE RD_S11 .800D0000 DEFINE RD_T3 .000E0000 DEFINE RD_T4 .800E0000 DEFINE RD_T5 .000F0000 DEFINE RD_T6 .800F0000 ;; First source registers ;; register_number << 15 DEFINE RS1_RA .00800000 DEFINE RS1_SP .00000100 DEFINE RS1_GP .00800100 DEFINE RS1_TP .00000200 DEFINE RS1_T0 .00800200 DEFINE RS1_T1 .00000300 DEFINE RS1_T2 .00800300 DEFINE RS1_S0 .00000400 DEFINE RS1_FP .00000400 DEFINE RS1_S1 .00800400 DEFINE RS1_A0 .00000500 DEFINE RS1_A1 .00800500 DEFINE RS1_A2 .00000600 DEFINE RS1_A3 .00800600 DEFINE RS1_A4 .00000700 DEFINE RS1_A5 .00800700 DEFINE RS1_A6 .00000800 DEFINE RS1_A7 .00800800 DEFINE RS1_S2 .00000900 DEFINE RS1_S3 .00800900 DEFINE RS1_S4 .00000A00 DEFINE RS1_S5 .00800A00 DEFINE RS1_S6 .00000B00 DEFINE RS1_S7 .00800B00 DEFINE RS1_S8 .00000C00 DEFINE RS1_S9 .00800C00 DEFINE RS1_S10 .00000D00 DEFINE RS1_S11 .00800D00 DEFINE RS1_T3 .00000E00 DEFINE RS1_T4 .00800E00 DEFINE RS1_T5 .00000F00 DEFINE RS1_T6 .00800F00 ;; Second source registers ;; register_number << 20 DEFINE RS2_RA .00001000 DEFINE RS2_SP .00002000 DEFINE RS2_GP .00003000 DEFINE RS2_TP .00004000 DEFINE RS2_T0 .00005000 DEFINE RS2_T1 .00006000 DEFINE RS2_T2 .00007000 DEFINE RS2_S0 .00008000 DEFINE RS2_FP .00008000 DEFINE RS2_S1 .00009000 DEFINE RS2_A0 .0000A000 DEFINE RS2_A1 .0000B000 DEFINE RS2_A2 .0000C000 DEFINE RS2_A3 .0000D000 DEFINE RS2_A4 .0000E000 DEFINE RS2_A5 .0000F000 DEFINE RS2_A6 .00000001 DEFINE RS2_A7 .00001001 DEFINE RS2_S2 .00002001 DEFINE RS2_S3 .00003001 DEFINE RS2_S4 .00004001 DEFINE RS2_S5 .00005001 DEFINE RS2_S6 .00006001 DEFINE RS2_S7 .00007001 DEFINE RS2_S8 .00008001 DEFINE RS2_S9 .00009001 DEFINE RS2_S10 .0000A001 DEFINE RS2_S11 .0000B001 DEFINE RS2_T3 .0000C001 DEFINE RS2_T4 .0000D001 DEFINE RS2_T5 .0000E001 DEFINE RS2_T6 .0000F001 DEFINE RS2_X0 .00000000 DEFINE RS2_X1 .00001000 DEFINE RS2_X2 .00002000 DEFINE RS2_X3 .00003000 DEFINE RS2_X4 .00004000 DEFINE RS2_X5 .00005000 DEFINE RS2_X6 .00006000 DEFINE RS2_X7 .00007000 DEFINE RS2_X8 .00008000 DEFINE RS2_X9 .00009000 DEFINE RS2_X10 .0000A000 DEFINE RS2_X11 .0000B000 DEFINE RS2_X12 .0000C000 DEFINE RS2_X13 .0000D000 DEFINE RS2_X14 .0000E000 DEFINE RS2_X15 .0000F000 DEFINE RS2_X16 .00000001 DEFINE RS2_X17 .00001001 DEFINE RS2_X18 .00002001 DEFINE RS2_X19 .00003001 DEFINE RS2_X20 .00004001 DEFINE RS2_X21 .00005001 DEFINE RS2_X22 .00006001 DEFINE RS2_X23 .00007001 DEFINE RS2_X24 .00008001 DEFINE RS2_X25 .00009001 DEFINE RS2_X26 .0000A001 DEFINE RS2_X27 .0000B001 DEFINE RS2_X28 .0000C001 DEFINE RS2_X29 .0000D001 DEFINE RS2_X30 .0000E001 DEFINE RS2_X31 .0000F001