55b42018db
This instruction is used to compare two registers and set the flags accordingly. In current architectures this is the same as r0-r1, but for RISCV it will be different. RISC-V does not have condition flags so (until a better solution) we are going to emulate them there. * module/mescc/armv4/as.scm (armv4:instructions): Add r0-cmp-r1 as alias of r0-r1. * module/mescc/i386/as.scm: Same. * module/mescc/x86_64/as.scm: Same. * module/mescc/compile.scm (expr->register): Make use of the new r0-cmp-r1 instruction. |
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| .. | ||
| armv4 | ||
| i386 | ||
| x86_64 | ||
| M1.scm | ||
| as.scm | ||
| bytevectors.scm | ||
| compile.scm | ||
| info.scm | ||
| mescc.scm | ||
| preprocess.scm | ||