W. J. van der Laan 55b42018db mescc: Add r0-cmp-r1 instruction. ... This instruction is used to compare two registers and set the flags accordingly. In current architectures this is the same as r0-r1, but for RISCV it will be different. RISC-V does not have condition flags so (until a better solution) we are going to emulate them there. * module/mescc/armv4/as.scm (armv4:instructions): Add r0-cmp-r1 as alias of r0-r1. * module/mescc/i386/as.scm: Same. * module/mescc/x86_64/as.scm: Same. * module/mescc/compile.scm (expr->register): Make use of the new r0-cmp-r1 instruction.		2023-09-12 11:04:10 +02:00
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as.scm	mescc: Add r0-cmp-r1 instruction.	2023-09-12 11:04:10 +02:00
info.scm	mescc: Add signed char.	2020-10-06 10:04:28 +02:00