Add M0.hex2.
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@ -2,7 +2,7 @@
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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targets = kaem-optional hex0 hex1 hex2 catm
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targets = kaem-optional hex0 hex1 hex2 catm M0
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cc = clang
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cflags = -ffreestanding -MMD -mno-red-zone -std=c11 -target x86_64-unknown-windows -masm=intel
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@ -109,7 +109,7 @@ DEFINE sub_rax, 83E8
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DEFINE sub_rbx, 4883EB
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DEFINE sub_rsp, 4883EC
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DEFINE sub_rax,rdx 4829D0
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DEFINE test_esi_esi 85F6
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DEFINE test_esi,esi 85F6
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DEFINE xor_eax,eax 31C0
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DEFINE xor_edx,edx 31D2
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DEFINE xor_esi,esi 31F6
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@ -496,7 +496,7 @@ DEFINE xor_r9,r9 4D31C9
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pop_r11 # restore r11
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# If the file ended (0 bytes read) return EOF
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test_esi_esi
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test_esi,esi
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jne %Read_byte_1
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mov_rax, %-4 # Put EOF in rax
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@ -118,7 +118,7 @@ F0 00 # SizeOfOptionalHeader
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# [0x148]
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# Start of section headers
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00 00 00 00 00 00 00 00 ; Name of the section (empty) but could set to ".text"
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2E 74 65 78 74 00 00 00 ; Name of the section: ".text"
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%PE32_end>PE32_text ; VirtualSize
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00 10 00 00 ; VirtualAddress
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%PE32_end>PE32_text ; SizeOfRawData
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@ -515,7 +515,7 @@ DD 06 00 00 ; SizeOfRawData
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415B ; pop_r11 # restore r11
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# If the file ended (0 bytes read) return EOF
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85F6 ; test_esi_esi
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85F6 ; test_esi,esi
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0F85 %y ; jne %Read_byte_1
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48C7C0 FCFFFFFF ; mov_rax, %-4 # Put EOF in rax
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@ -26,3 +26,11 @@ amd64\artifact\hex1.efi amd64\hex2.hex1 amd64\artifact\hex2-0.efi
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amd64\artifact\hex2-0.efi amd64\catm.hex2 amd64\artifact\catm.efi
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# catm removes the need for cat or shell support for redirection by providing
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# equivalent functionality via catm output_file input1 input2 ... inputN
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###############################
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# Phase-3 Build M0 from hex2 #
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###############################
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amd64\artifact\catm.efi amd64\artifact\M0.hex2 amd64\PE32-amd64.hex2 amd64\M0.hex2
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amd64\artifact\hex2-0.efi amd64\artifact\M0.hex2 amd64\artifact\M0.efi
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# M0 is the architecture specific version of M1 and is by design single
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# architecture only and will be replaced by the C code version of M1
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