2016-06-04 18:44:44 +01:00
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* Instruction Listing
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** 00 xx xx xx :: NOP
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2016-05-30 02:45:08 +01:00
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00 00 00 00 # Proper NOP
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00 xx xx xx # NOP equivelent, although these instructions will all be treated as NOPs. DO NOT USE THEM.
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2016-06-04 18:44:44 +01:00
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** 4OP Groups
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4OP nn is the XOP, a = b OP c Cond d
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*** 01 nn ab cd :: 4OP Integer group
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2016-05-30 22:52:42 +01:00
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01 00 ab cd # ADD.CI a b c d :: a = b + c + CARRY? d [signed]
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01 01 ab cd # ADD.CO a b c d :: a = b + c; d = CARRY? [signed]
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01 02 ab cd # ADD.CIO a b c d :: a = b + c + CARRY? d; d = CARRY? [signed]
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01 03 ab cd # ADDU.CI a b c d :: a = b + c + CARRY? d [unsigned]
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01 04 ab cd # ADDU.CO a b c d :: a = b + c; d = CARRY? [unsigned]
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01 05 ab cd # ADDU.CIO a b c d :: a = b + c + CARRY? d; d = CARRY? [unsigned]
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01 06 ab cd # SUB.BI a b c d :: a = b - c - BORROW? d [signed]
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01 07 ab cd # SUB.BO a b c d :: a = b - c; d = BORROW? [signed]
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01 08 ab cd # SUB.BIO a b c d :: a = b - c - BORROW? d; d = BORROW? [signed]
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01 09 ab cd # SUBU.BI a b c d :: a = b - c - BORROW? d [unsigned]
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01 0A ab cd # SUBU.BO a b c d :: a = b - c; d = BORROW? [unsigned]
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01 0B ab cd # SUBU.BIO a b c d :: a = b - c - BORROW? d; d = BORROW? [unsigned]
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01 0C ab cd # MULTIPLY a b c d :: a = MUL c d; b = MULH c d [signed]
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01 0D ab cd # MULTIPLYU a b c d :: a = MUL c d; b = MULH c d [unsigned]
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01 0E ab cd # DIVIDE a b c d :: a = DIV c d; b = MOD c d [signed]
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01 0F ab cd # DIVIDEU a b c d :: a = DIV c d; b = MOD c d [unsigned]
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01 10 ab cd # MUX a b c d :: a = (c & ~b) | (d & b)
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01 11 ab cd # NMUX a b c d :: a = (c & b) | (d & ~b)
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01 12 ab cd # SORT a b c d :: a = MAX(c, d); b = MIN(c, d) [signed]
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01 13 ab cd # SORTU a b c d :: a = MAX(c, d); b = MIN(c, d) [unsigned]
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2016-06-04 18:44:44 +01:00
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**** Reserved Block
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2016-05-30 22:52:42 +01:00
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01 14 xx xx # Reserved
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...
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01 FF xx xx # Reserved
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2016-06-04 18:44:44 +01:00
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*** 02 nn ab cd :: 4OP Floating group
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*** 03 nn ab cd :: 4OP SIMD group
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*** 04 nn ab cd :: 4OP Reserved group
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2016-05-30 02:45:08 +01:00
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2016-06-04 18:44:44 +01:00
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** 3OP Groups
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3OP nn n is the XOP, a = b OP c
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*** 05 nn na bc :: 3OP Integer group
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2016-05-30 02:45:08 +01:00
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05 00 0a bc # ADD a b c :: a = b + c [signed]
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05 00 1a bc # ADDU a b c :: a = b + c [unsigned]
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05 00 2a bc # SUB a b c :: a = b - c [signed]
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05 00 3a bc # SUBU a b c :: a = b - c [unsigned]
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05 00 4a bc # CMP a b c :: a = b CMP c [signed]
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05 00 5a bc # CMPU a b c :: a = b CMP c [unsigned]
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05 00 6a bc # MUL a b c :: a = b * c [signed] bottom n bits
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05 00 7a bc # MULH a b c :: a = (b * c) >> n [signed] top n bits
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05 00 8a bc # MULU a b c :: a = b * c [unsigned] bottom n bits
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05 00 9a bc # MULUH a b c :: a = (b * c) >> n [unsigned] top n bits
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05 00 Aa bc # DIV a b c :: a = b / c [signed]
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05 00 Ba bc # MOD a b c :: a = b % c [signed]
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05 00 Ca bc # DIVU a b c :: a = b / c [unsigned]
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05 00 Da bc # MODU a b c :: a = b % c [unsigned]
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05 00 Ex xx # Reserved
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05 00 Fx xx # Reserved
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05 01 0a bc # MAX a b c :: a = MAX(b, c) [signed]
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05 01 1a bc # MAXU a b c :: a = MAX(b, c) [unsigned]
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05 01 2a bc # MIN a b c :: a = MIN(b, c) [signed]
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05 01 3a bc # MINU a b c :: a = MIN(b, c) [unsigned]
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05 01 4a bc # PACK a b c :: a = PACK(b, c)
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05 01 5a bc # UNPACK a b c :: a = UNPACK(b, c)
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05 01 6a bc # PACK8.CO a b c :: a = PACK(b) c = Overload? [signed]
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05 01 7a bc # PACK8U.CO a b c :: a = PACK(b) c = Overload? [unsigned]
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05 01 8a bc # PACK16.CO a b c :: a = PACK(b) c = Overload? [signed]
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05 01 9a bc # PACK16U.CO a b c :: a = PACK(b) c = Overload? [unsigned]
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05 01 Aa bc # PACK32.CO a b c :: a = PACK(b) c = Overload? [signed]
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05 01 Ba bc # PACK32U.CO a b c :: a = PACK(b) c = Overload? [unsigned]
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2016-05-30 15:58:23 +01:00
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05 01 Ca bc # Reserved
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05 01 Da bc # Reserved
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2016-05-30 02:45:08 +01:00
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05 01 Ex xx # Reserved
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05 01 Fx xx # Reserved
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05 02 0a bc # AND a b c :: a = b & c
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05 02 1a bc # OR a b c :: a = b | c
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05 02 2a bc # XOR a b c :: a = b XOR c
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05 02 3a bc # NAND a b c :: a != b & c
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05 02 4a bc # NOR a b c :: a != b | c
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05 02 5a bc # XNOR a b c :: a != b XOR c
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05 02 6a bc # MPQ a b c :: a = b MPQ c [Converse Nonimplication]
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05 02 7a bc # LPQ a b c :: a = b LPQ c [Material Nonimplication]
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05 02 8a bc # CPQ a b c :: a = b CPQ c [Material Implication]
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05 02 8a bc # BPQ a b c :: a = b BPQ c [Converse Implication]
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05 02 9x xx # Reserved
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...
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05 02 Fx xx # Reserved
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05 03 0a bc # SAL a b c :: a = b >> c [arithmetically]
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05 03 1a bc # SAR a b c :: a = b << c [arithmetically]
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05 03 2a bc # SL0 a b c :: a = b >> c [Fill with zeros]
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05 03 3a bc # SR0 a b c :: a = b << c [Fill with zeros]
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05 03 4a bc # SL1 a b c :: a = b >> c [Fill with ones]
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05 03 5a bc # SR1 a b c :: a = b << c [Fill with ones]
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05 03 6a bc # ROL a b c :: a = ROL(b, c) [Circular rotate left]
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05 03 7a bc # ROR a b c :: a = ROR(b, c) [Circular rotate right]
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2016-06-04 18:44:44 +01:00
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**** Reserved
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2016-05-30 02:45:08 +01:00
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05 03 8x xx # Reserved
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...
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05 FF Fx xx # Reserved
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2016-06-04 18:44:44 +01:00
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*** 06 nn na bc :: 3OP Floating group
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*** 07 nn na bc :: 3OP SIMD group
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*** 08 nn na bc :: 3OP Reserved group
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** 2OP Groups
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2OP nn nn is the XOP, a = OP b
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*** 09 nn nn ab :: 2OP Integer group
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2016-05-30 02:45:08 +01:00
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09 00 00 ab # NEG a b :: a = (b > 0) ? -b : b
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09 00 01 ab # ABS a b :: a = |b|
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09 00 02 ab # NABS a b :: a = -|b|
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09 00 03 ab # SWAP a b :: a <=> b
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09 00 04 ab # COPY a b :: a = b
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09 00 05 ab # MOVE a b :: a = b; b = 0
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09 00 06 xx # Reserved
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...
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09 00 FF xx # Reserved
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2016-05-30 17:38:02 +01:00
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09 01 00 ab # BRANCH a b :: MEM[b] = PC; PC = a
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09 01 01 ab # CALL a b :: MEM[b] = PC; b = b + (register size in bytes); PC = a
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2016-06-04 18:44:44 +01:00
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**** Reserved
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2016-05-30 17:38:02 +01:00
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09 01 02 xx # Reserved
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2016-05-30 02:45:08 +01:00
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...
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09 FF FF xx # Reserved
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2016-06-04 18:44:44 +01:00
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*** 0A nn nn ab :: 2OP Floating group
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*** 0B nn nn ab :: 2OP SIMD group
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*** 0C nn nn ab :: 2OP Reserved group
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** 1OP Groups
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1OP nn nn n is the XOP, a = OP a
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*** 0D nn nn na :: 1OP group
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2016-05-30 02:45:08 +01:00
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0D 00 00 0a # READPC a :: a = PC
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0D 00 00 1a # READSCID a :: a = SCID
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0D 00 00 2a # FALSE a :: a = 0
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0D 00 00 3a # TRUE a :: a = FF ... FF
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0D 00 00 4x # Reserved
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...
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0D 00 FF Fx # Reserved
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0D 01 00 0a # JSR_COROUTINE a; PC = a
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2016-05-30 17:38:02 +01:00
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0D 01 00 1a # RET a :: PC = MEM[a]; a = a - (register size in bytes)
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0D 01 00 2x # Reserved
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...
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0D 01 FF Fx # Reserved
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0D 02 00 0a # PUSHPC a :: MEM[a] = PC; a = a + (register size in bytes)
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0D 02 00 1a # POPPC a :: PC = MEM[a]; a = a - (register size in bytes)
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2016-06-04 18:44:44 +01:00
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**** Reserved
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2016-05-30 17:38:02 +01:00
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0D 02 00 2x # Reserved
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2016-05-30 02:45:08 +01:00
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...
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0D FF FF Fx # Reserved
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2016-06-04 18:44:44 +01:00
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** 2OPI Groups
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2OPI ii ii is the Immediate, a = b OP ii ii
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*** 2OPI Integer
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2016-05-30 02:45:08 +01:00
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0E ab ii ii # ADDI a b ii ii :: a = b + ii ii [signed]
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0F ab ii ii # ADDUI a b ii ii :: a = b + ii ii [unsigned]
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10 ab ii ii # SUBI a b ii ii :: a = b - ii ii [signed]
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11 ab ii ii # SUBUI a b ii ii :: a = b - ii ii [unsigned]
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2016-06-04 18:44:44 +01:00
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*** 2OPI Integer signed compare
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2016-05-30 02:45:08 +01:00
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12 ab ii ii # CMPI a b ii ii :: a = b CMP ii ii [signed]
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2016-06-04 18:44:44 +01:00
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*** 2OPI Integer Load
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2016-05-30 02:45:08 +01:00
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13 ab ii ii # LOAD a b ii ii :: a = MEM[b + ii ii]
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14 ab ii ii # LOAD8 a b ii ii :: a = MEM[b + ii ii] [signed 8bits]
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15 ab ii ii # LOADU8 a b ii ii :: a = MEM[b + ii ii] [unsigned 8bits]
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16 ab ii ii # LOAD16 a b ii ii :: a = MEM[b + ii ii] [signed 16bits]
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17 ab ii ii # LOADU16 a b ii ii :: a = MEM[b + ii ii] [unsigned 16bits]
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18 ab ii ii # LOAD32 a b ii ii :: a = MEM[b + ii ii] [signed 32bits]
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19 ab ii ii # LOADU32 a b ii ii :: a = MEM[b + ii ii] [unsigned 32bits]
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2016-05-30 15:58:23 +01:00
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1A ab ii ii # Reserved
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1B ab ii ii # Reserved
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2016-05-30 02:45:08 +01:00
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1C ab ii ii # Reserved
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1D ab ii ii # Reserved
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1E ab ii ii # Reserved
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2016-06-04 18:44:44 +01:00
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*** 2OPI Integer unsigned compare
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2016-05-30 02:45:08 +01:00
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1F ab ii ii # CMPUI a b ii ii :: a = b CMP ii ii [unsigned]
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2016-06-04 18:44:44 +01:00
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*** 2OPI Integer store
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2016-05-30 02:45:08 +01:00
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20 ab ii ii # STORE a b ii :: MEM[b + ii ii] = a
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21 ab ii ii # STORE8 a b ii :: MEM[b + ii ii] = a [signed 8bits]
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22 ab ii ii # STOREU8 a b ii :: MEM[b + ii ii] = a [unsigned 8bits]
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23 ab ii ii # STORE16 a b ii :: MEM[b + ii ii] = a [signed 16bits]
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24 ab ii ii # STOREU16 a b ii :: MEM[b + ii ii] = a [unsigned 16bits]
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25 ab ii ii # STORE32 a b ii :: MEM[b + ii ii] = a [signed 32bits]
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26 ab ii ii # STOREU32 a b ii :: MEM[b + ii ii] = a [unsigned 32bits]
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2016-05-30 15:58:23 +01:00
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27 ab ii ii # Reserved
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28 ab ii ii # Reserved
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2016-05-30 02:45:08 +01:00
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29 ab ii ii # Reserved
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2A ab ii ii # Reserved
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2B ab ii ii # Reserved
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2016-06-04 18:44:44 +01:00
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** 1OPI Groups
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1OPI i ii ii is the Immediate, a = a OP i ii ii
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*** Conditional Jumps
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2016-05-30 02:45:08 +01:00
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2C ai ii ii # JUMP.C a i ii ii :: Carry? a; PC = PC + i ii ii
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2D ai ii ii # JUMP.B a i ii ii :: Borrow? a; PC = PC + i ii ii
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2E ai ii ii # JUMP.O a i ii ii :: Overflow? a; PC = PC + i ii ii
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2F ai ii ii # JUMP.G a i ii ii :: GT? a; PC = PC + i ii ii
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30 ai ii ii # JUMP.GE a i ii ii :: GT? a | EQ? a; PC = PC + i ii ii
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31 ai ii ii # JUMP.E a i ii ii :: EQ? a; PC = PC + i ii ii
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32 ai ii ii # JUMP.NE a i ii ii :: NEQ? a; PC = PC + i ii ii
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33 ai ii ii # JUMP.LE a i ii ii :: LT? a | EQ? a; PC = PC + i ii ii
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34 ai ii ii # JUMP.L a i ii ii :: LT? a; PC = PC + i ii ii
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35 ai ii ii # JUMP.Z a i ii ii :: ZERO? a; PC = PC + i ii ii
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36 ai ii ii # JUMP.NZ a i ii ii :: NZERO? a; PC = PC + i ii ii
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37 xx xx xx # Reserved
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38 xx xx xx # Reserved
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39 xx xx xx # Reserved
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3A xx xx xx # Reserved
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3B xx xx xx # Reserved
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2016-06-04 18:44:44 +01:00
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** 0OPI group
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0OPI ii ii ii is the Immediate, OP ii ii ii
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*** Unconditional jumps
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2016-05-30 02:45:08 +01:00
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3C ii ii ii # JUMP ii ii ii :: PC = PC + ii ii ii
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2016-06-04 18:44:44 +01:00
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** Reserved Block 0
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At this time these instructions only produce a warning; but could do anything.
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DO NOT USE.
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3D 00 00 00 # Reserved
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2016-05-30 02:45:08 +01:00
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...
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2016-06-04 18:44:44 +01:00
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41 FF FF FF # Reserve
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** HALCODE Group
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42 hh hh hh is the HALCODE callID, invalid HALCODE SHOULD NOT BE USED.
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2016-05-30 02:45:08 +01:00
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2016-06-04 18:44:44 +01:00
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*** HALCODE Reserved for Operating Systems
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The following block contains both instructions that are reserved for Operating systems and for internal use by Operating systems
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2016-06-04 17:05:10 +01:00
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42 00 xx xx # Reserved
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...
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42 0F xx xx # Reserved
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2016-06-04 18:44:44 +01:00
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*** Tape console HALCODE
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This HALCODE is used for interacting with any tape console attached to the system.
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**** Reference specific notes
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In this reference implementation we will be interacting with a simplified version of the series 10 console.
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All compatible implementations need to ensure to implement functional equivelents.
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Provided of course that any deviations would not change any output specified to be written to tape.
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Padding with Zeros til start/end of page/segment however is acceptable.
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**** Standard compatibility requirements
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The following 3 devices must exist with the following exact IDs
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Keyboard/tty :: 00 00 00 00
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Tape 1 :: 00 00 11 00
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Tape 2 :: 00 00 11 01
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**** Required Device HALCODE
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2016-06-04 17:05:10 +01:00
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42 10 00 00 # FOPEN :: Feed on device who's ID matches the contents register 0 until first non-zero byte is found.
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42 10 00 01 # FCLOSE :: Close out writes to device who's ID matches the contents of register 0.
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42 10 00 02 # FSEEK :: seek forward or backward the number of bytes specified in register 1 on the device who's ID matches the contents of register 0.
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42 10 00 03 # REWIND :: rewind back to first non-zero byte found on tape.
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2016-06-04 18:44:44 +01:00
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**** Reserved Block for Hardware specific implementation details
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2016-06-04 17:05:10 +01:00
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42 10 00 04 # Reserved
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...
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42 10 00 FF # Reserved
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2016-06-04 18:44:44 +01:00
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**** Required Device capability HALCODE
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***** Device Read HALCODE
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2016-06-04 17:05:10 +01:00
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42 10 01 00 # FGETC :: read 1 byte into register 0 from device who's ID is in register 1
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2016-06-04 18:44:44 +01:00
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***** Reserved Block for Hardware specific implementation details
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2016-06-04 17:05:10 +01:00
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42 10 01 01 # Reserved
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...
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42 10 01 FF # Reserved
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2016-06-04 18:44:44 +01:00
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***** Device Write HALCODE
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2016-06-04 17:05:10 +01:00
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42 10 02 00 # FPUTC :: write 1 byte from register 0 to device who's ID is in register 1
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2016-06-04 18:44:44 +01:00
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***** Reserved Block for Hardware specific implementation details
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42 10 02 01 # Reserved
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...
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42 10 02 FF # Reserved
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**** Reserved Block for Future HALCODE Expansion
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42 10 03 00 # Reserved
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...
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42 FF FF FF # Reserved
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2016-05-30 02:45:08 +01:00
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2016-06-04 18:44:44 +01:00
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** Reserved Block 1
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At this time these instructions only produce a warning; but could do anything.
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DO NOT USE.
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43 00 00 00 # Reserved
|
2016-05-30 02:45:08 +01:00
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...
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2016-06-04 18:44:44 +01:00
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FE FF FF FF # Reserved
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2016-05-30 02:45:08 +01:00
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2016-06-04 18:44:44 +01:00
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** 0OP
|
2016-05-30 02:45:08 +01:00
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FF xx xx xx # HALT equivelent, although these instructions will all be treated as HALTs. DO NOT USE THEM.
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FF FF FF FF # Proper HALT
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2016-06-04 18:44:44 +01:00
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* Encoding/Decoding Reference
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** Registers
|
2016-05-30 03:51:41 +01:00
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There is a direct and consistent relationship between the nybbles and the registers.
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Reg0 -> 0, Reg1 -> 1, ... Reg14 -> E, Reg15 -> F
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