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Incorporated Bitshifting instructions

This commit is contained in:
Jeremiah Orians 2016-06-06 19:32:43 -04:00
parent 7ce6a98931
commit 2bb7ba3038
No known key found for this signature in database
GPG Key ID: 7457821534D2ACCD
5 changed files with 120 additions and 6 deletions
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18
ISA_HEX_Map.org
View File

@ -107,12 +107,12 @@
05 02 Fx xx # Reserved
**** Bit rotation group
05 03 0a bc # SAL a b c :: a = b >> c [arithmetically]
05 03 1a bc # SAR a b c :: a = b << c [arithmetically]
05 03 2a bc # SL0 a b c :: a = b >> c [Fill with zeros]
05 03 3a bc # SR0 a b c :: a = b << c [Fill with zeros]
05 03 4a bc # SL1 a b c :: a = b >> c [Fill with ones]
05 03 5a bc # SR1 a b c :: a = b << c [Fill with ones]
05 03 0a bc # SAL a b c :: a = b << c [arithmetically]
05 03 1a bc # SAR a b c :: a = b >> c [arithmetically]
05 03 2a bc # SL0 a b c :: a = b << c [Fill with zeros]
05 03 3a bc # SR0 a b c :: a = b >> c [Fill with zeros]
05 03 4a bc # SL1 a b c :: a = b << c [Fill with ones]
05 03 5a bc # SR1 a b c :: a = b >> c [Fill with ones]
05 03 6a bc # ROL a b c :: a = ROL(b, c) [Circular rotate left]
05 03 7a bc # ROR a b c :: a = ROR(b, c) [Circular rotate right]
@ -257,6 +257,12 @@
2D 0a ii ii # CALLI a ii ii :: MEM[a] = PC; a = a + (register size in bytes); PC = PC + ii ii
2D 1a ii ii # LOADI a ii ii :: a = ii ii (signed)
2D 2a ii ii # LOADUI a ii ii :: a = ii ii (unsigned)
2D 3a ii ii # SALI a ii ii :: a = a << ii ii [arithmetically]
2D 4a ii ii # SARI a ii ii :: a = a >> ii ii [arithmetically]
2D 5a ii ii # SL0I a ii ii :: a = a << ii ii [Fill with zeros]
2D 6a ii ii # SR0I a ii ii :: a = a >> ii ii [Fill with zeros]
2D 7a ii ii # SL1I a ii ii :: a = a << ii ii [Fill with ones]
2D 8a ii ii # SR1I a ii ii :: a = a >> ii ii [Fill with ones]
** 0OPI group
0OPI ii ii is the Immediate, OP ii ii

6
asm.c
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@ -290,6 +290,12 @@ void assemble(struct Token* p)
setExpression(p, "CALLI", "2D0", 4);
setExpression(p, "LOADI", "2D1", 4);
setExpression(p, "LOADUI", "2D2", 4);
setExpression(p, "SALI", "2D3", 4);
setExpression(p, "SARI", "2D4", 4);
setExpression(p, "SL0I", "2D5", 4);
setExpression(p, "SR0I", "2D6", 4);
setExpression(p, "SL1I", "2D7", 4);
setExpression(p, "SR1I", "2D8", 4);
/* 0OPI Group */
setExpression(p, "JUMP", "3C00", 4);

30
disasm.c
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@ -857,6 +857,36 @@ void decode_Branch_1OPI(struct Instruction* c)
strncpy(Name, "LOADUI", 19);
break;
}
case 0x3: /* SALI */
{
strncpy(Name, "SALI", 19);
break;
}
case 0x4: /* SARI */
{
strncpy(Name, "SARI", 19);
break;
}
case 0x5: /* SL0I */
{
strncpy(Name, "SL0I", 19);
break;
}
case 0x6: /* SR0I */
{
strncpy(Name, "SR0I", 19);
break;
}
case 0x7: /* SL1I */
{
strncpy(Name, "SL1I", 19);
break;
}
case 0x8: /* SR1I */
{
strncpy(Name, "SR1I", 19);
break;
}
default: /* Unknown 1OPI*/
{
break;

36
vm.c
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@ -747,26 +747,32 @@ bool eval_3OP_Int(struct lilith* vm, struct Instruction* c)
}
case 0x030: /* SAL */
{
vm->reg[c->reg0] = vm->reg[c->reg1] << vm->reg[c->reg2];
break;
}
case 0x031: /* SAR */
{
vm->reg[c->reg0] = vm->reg[c->reg1] >> vm->reg[c->reg2];
break;
}
case 0x032: /* SL0 */
{
vm->reg[c->reg0] = shift_register(vm->reg[c->reg1], vm->reg[c->reg2], true, true);
break;
}
case 0x033: /* SR0 */
{
vm->reg[c->reg0] = shift_register(vm->reg[c->reg1], vm->reg[c->reg2], false, true);
break;
}
case 0x034: /* SL1 */
{
vm->reg[c->reg0] = shift_register(vm->reg[c->reg1], vm->reg[c->reg2], true, false);
break;
}
case 0x035: /* SR1 */
{
vm->reg[c->reg0] = shift_register(vm->reg[c->reg1], vm->reg[c->reg2], false, false);
break;
}
case 0x036: /* ROL */
@ -1246,6 +1252,36 @@ bool eval_branch_1OPI(struct lilith* vm, struct Instruction* c)
vm->reg[c->reg0] = c->raw_Immediate;
break;
}
case 0x3: /* SALI */
{
vm->reg[c->reg0] = vm->reg[c->reg0] << c->raw_Immediate;
break;
}
case 0x4: /* SARI */
{
vm->reg[c->reg0] = vm->reg[c->reg0] >> c->raw_Immediate;
break;
}
case 0x5: /* SL0I */
{
vm->reg[c->reg0] = shift_register(vm->reg[c->reg0], c->raw_Immediate, true, true);
break;
}
case 0x6: /* SR0I */
{
vm->reg[c->reg0] = shift_register(vm->reg[c->reg0], c->raw_Immediate, false, true);
break;
}
case 0x7: /* SL1I */
{
vm->reg[c->reg0] = shift_register(vm->reg[c->reg0], c->raw_Immediate, true, false);
break;
}
case 0x8: /* SR1I */
{
vm->reg[c->reg0] = shift_register(vm->reg[c->reg0], c->raw_Immediate, false, false);
break;
}
default: return true;
}
return false;

36
vm.h
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@ -167,6 +167,7 @@ void unpack_byte(uint8_t a, char* c)
c[1] = table[a % 16];
}
/* Unpack the full instruction */
void unpack_instruction(struct Instruction* c)
{
unpack_byte(c->raw0, &(c->operation[0]));
@ -177,6 +178,7 @@ void unpack_instruction(struct Instruction* c)
c->opcode[1] = c->operation[1];
}
/* Correctly write out bytes on little endian hardware */
void writeout_Reg(struct lilith* vm, uint32_t p, uint32_t value)
{
uint8_t raw0, raw1, raw2, raw3;
@ -195,6 +197,7 @@ void writeout_Reg(struct lilith* vm, uint32_t p, uint32_t value)
vm->memory[p + 3] = raw3;
}
/* Allow the use of native data format for Register operations */
uint32_t readin_Reg(struct lilith* vm, uint32_t p)
{
uint8_t raw0, raw1, raw2, raw3, sum;
@ -210,3 +213,36 @@ uint32_t readin_Reg(struct lilith* vm, uint32_t p)
return sum;
}
/* Determine the result of bit shifting */
uint32_t shift_register(uint32_t source, uint32_t amount, bool left, bool zero)
{
uint32_t tmp = source;
if(left)
{
while( amount > 0 )
{
tmp = tmp * 2;
amount = amount - 1;
if(!zero)
{
tmp = tmp + 1;
}
}
}
else
{
while( amount > 0 )
{
tmp = tmp / 2;
amount = amount - 1;
if(!zero)
{
tmp = tmp | (1 << 31);
}
}
}
return tmp;
}