x86-asm: Get rid of OPC_JMP and OPC_SHORTJMP
Those two insn types are nicer to handle as operand types, because the pressure for bits on instr_type is higher than for operands.
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4094f7c5fc
commit
e2f489aaff
20
i386-asm.c
20
i386-asm.c
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@ -41,12 +41,8 @@
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#define OPC_ARITH 0x30 /* arithmetic opcodes */
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#define OPC_FARITH 0x40 /* FPU arithmetic opcodes */
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#define OPC_TEST 0x50 /* test opcodes */
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#define OPC_JMP_TEST 0x60 /* A test and jmp opcode */
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#define OPC_JMP 0x70 /* A non-testing jmp opcode */
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#define OPCT_IS(v,i) (((v) & OPCT_MASK) == (i))
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#define OPC_SHORTJMP 0x80 /* short jmp operand */
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#define OPC_0F 0x100 /* Is secondary map (0x0f prefix) */
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#ifdef TCC_TARGET_X86_64
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# define OPC_WLQ 0x1000 /* accepts w, l, q or no suffix */
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@ -96,6 +92,8 @@ enum {
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OPT_REGW, /* REG16 | REG32 | REG64 */
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OPT_IMW, /* IM16 | IM32 */
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OPT_MMXSSE, /* MMX | SSE */
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OPT_DISP, /* Like OPT_ADDR, but emitted as displacement (for jumps) */
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OPT_DISP8, /* Like OPT_ADDR, but only 8bit (short jumps) */
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/* can be ored with any OPT_xxx */
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OPT_EA = 0x80
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};
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@ -627,7 +625,7 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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if (!(opcode >= pa->sym && opcode < pa->sym + 7*NBWLX))
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continue;
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s = (opcode - pa->sym) % NBWLX;
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} else if (it == OPC_TEST || it == OPC_JMP_TEST) {
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} else if (it == OPC_TEST) {
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if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
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continue;
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/* cmovxx is a test opcode but accepts multiple sizes.
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@ -687,6 +685,10 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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case OPT_MMXSSE:
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v = OP_MMX | OP_SSE;
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break;
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case OPT_DISP:
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case OPT_DISP8:
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v = OP_ADDR;
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break;
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default:
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v = 1 << op2;
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break;
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@ -833,7 +835,7 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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}
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if (pa->instr_type & OPC_B)
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v += s >= 1;
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if (pa->instr_type & OPC_SHORTJMP) {
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if (nb_ops == 1 && pa->op_type[0] == OPT_DISP8) {
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Sym *sym;
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int jmp_disp;
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@ -861,8 +863,7 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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tcc_error("invalid displacement");
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}
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}
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if (OPCT_IS(pa->instr_type, OPC_TEST)
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|| OPCT_IS(pa->instr_type, OPC_JMP_TEST))
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if (OPCT_IS(pa->instr_type, OPC_TEST))
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v += test_bits[opcode - pa->sym];
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op1 = v >> 16;
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if (op1)
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@ -955,8 +956,7 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode)
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} else if (v & OP_IM64) {
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gen_expr64(&ops[i].e);
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#endif
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} else if (OPCT_IS (pa->instr_type, OPC_JMP)
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|| OPCT_IS (pa->instr_type, OPC_JMP_TEST)) {
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} else if (pa->op_type[i] == OPT_DISP || pa->op_type[i] == OPT_DISP8) {
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gen_disp32(&ops[i].e);
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} else {
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gen_expr32(&ops[i].e);
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18
i386-asm.h
18
i386-asm.h
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@ -200,9 +200,9 @@ ALT(DEF_ASM_OP3(shrdw, 0x0fad, 0, OPC_MODRM | OPC_WLX, OPT_CL, OPT_REGW, OPT_EA
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ALT(DEF_ASM_OP2(shrdw, 0x0fad, 0, OPC_MODRM | OPC_WLX, OPT_REGW, OPT_EA | OPT_REGW))
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ALT(DEF_ASM_OP1(call, 0xff, 2, OPC_MODRM, OPT_INDIR))
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ALT(DEF_ASM_OP1(call, 0xe8, 0, OPC_JMP, OPT_ADDR))
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ALT(DEF_ASM_OP1(call, 0xe8, 0, 0, OPT_DISP))
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ALT(DEF_ASM_OP1(jmp, 0xff, 4, OPC_MODRM, OPT_INDIR))
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ALT(DEF_ASM_OP1(jmp, 0xeb, 0, OPC_SHORTJMP | OPC_JMP, OPT_ADDR))
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ALT(DEF_ASM_OP1(jmp, 0xeb, 0, 0, OPT_DISP8))
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ALT(DEF_ASM_OP2(lcall, 0x9a, 0, 0, OPT_IM16, OPT_IM32))
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ALT(DEF_ASM_OP1(lcall, 0xff, 3, OPC_MODRM, OPT_EA))
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@ -221,13 +221,13 @@ ALT(DEF_ASM_OP1(ret, 0xc2, 0, 0, OPT_IM16))
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DEF_ASM_OP0(lret, 0xcb)
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ALT(DEF_ASM_OP1(lret, 0xca, 0, 0, OPT_IM16))
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ALT(DEF_ASM_OP1(jo, 0x70, 0, OPC_SHORTJMP | OPC_JMP_TEST, OPT_ADDR))
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DEF_ASM_OP1(loopne, 0xe0, 0, OPC_SHORTJMP, OPT_ADDR)
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DEF_ASM_OP1(loopnz, 0xe0, 0, OPC_SHORTJMP, OPT_ADDR)
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DEF_ASM_OP1(loope, 0xe1, 0, OPC_SHORTJMP, OPT_ADDR)
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DEF_ASM_OP1(loopz, 0xe1, 0, OPC_SHORTJMP, OPT_ADDR)
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DEF_ASM_OP1(loop, 0xe2, 0, OPC_SHORTJMP, OPT_ADDR)
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DEF_ASM_OP1(jecxz, 0xe3, 0, OPC_SHORTJMP, OPT_ADDR)
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ALT(DEF_ASM_OP1(jo, 0x70, 0, OPC_TEST, OPT_DISP8))
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DEF_ASM_OP1(loopne, 0xe0, 0, 0, OPT_DISP8)
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DEF_ASM_OP1(loopnz, 0xe0, 0, 0, OPT_DISP8)
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DEF_ASM_OP1(loope, 0xe1, 0, 0, OPT_DISP8)
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DEF_ASM_OP1(loopz, 0xe1, 0, 0, OPT_DISP8)
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DEF_ASM_OP1(loop, 0xe2, 0, 0, OPT_DISP8)
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DEF_ASM_OP1(jecxz, 0xe3, 0, 0, OPT_DISP8)
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/* float */
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/* specific fcomp handling */
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18
x86_64-asm.h
18
x86_64-asm.h
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@ -207,9 +207,9 @@ ALT(DEF_ASM_OP3(shrdw, 0x0fad, 0, OPC_MODRM | OPC_WLX, OPT_CL, OPT_REGW, OPT_EA
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ALT(DEF_ASM_OP2(shrdw, 0x0fad, 0, OPC_MODRM | OPC_WLX, OPT_REGW, OPT_EA | OPT_REGW))
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ALT(DEF_ASM_OP1(call, 0xff, 2, OPC_MODRM, OPT_INDIR))
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ALT(DEF_ASM_OP1(call, 0xe8, 0, OPC_JMP, OPT_ADDR))
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ALT(DEF_ASM_OP1(call, 0xe8, 0, 0, OPT_DISP))
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ALT(DEF_ASM_OP1(jmp, 0xff, 4, OPC_MODRM, OPT_INDIR))
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ALT(DEF_ASM_OP1(jmp, 0xeb, 0, OPC_SHORTJMP | OPC_JMP, OPT_ADDR))
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ALT(DEF_ASM_OP1(jmp, 0xeb, 0, 0, OPT_DISP8))
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ALT(DEF_ASM_OP1(lcall, 0xff, 3, OPC_MODRM, OPT_EA))
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ALT(DEF_ASM_OP1(ljmp, 0xff, 5, OPC_MODRM, OPT_EA))
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@ -226,13 +226,13 @@ ALT(DEF_ASM_OP1(ret, 0xc2, 0, 0, OPT_IM16))
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DEF_ASM_OP0(lret, 0xcb)
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ALT(DEF_ASM_OP1(lret, 0xca, 0, 0, OPT_IM16))
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ALT(DEF_ASM_OP1(jo, 0x70, 0, OPC_SHORTJMP | OPC_JMP_TEST, OPT_ADDR))
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DEF_ASM_OP1(loopne, 0xe0, 0, OPC_SHORTJMP, OPT_ADDR)
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DEF_ASM_OP1(loopnz, 0xe0, 0, OPC_SHORTJMP, OPT_ADDR)
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DEF_ASM_OP1(loope, 0xe1, 0, OPC_SHORTJMP, OPT_ADDR)
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DEF_ASM_OP1(loopz, 0xe1, 0, OPC_SHORTJMP, OPT_ADDR)
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DEF_ASM_OP1(loop, 0xe2, 0, OPC_SHORTJMP, OPT_ADDR)
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DEF_ASM_OP1(jecxz, 0x67e3, 0, OPC_SHORTJMP, OPT_ADDR)
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ALT(DEF_ASM_OP1(jo, 0x70, 0, OPC_TEST, OPT_DISP8))
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DEF_ASM_OP1(loopne, 0xe0, 0, 0, OPT_DISP8)
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DEF_ASM_OP1(loopnz, 0xe0, 0, 0, OPT_DISP8)
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DEF_ASM_OP1(loope, 0xe1, 0, 0, OPT_DISP8)
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DEF_ASM_OP1(loopz, 0xe1, 0, 0, OPT_DISP8)
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DEF_ASM_OP1(loop, 0xe2, 0, 0, OPT_DISP8)
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DEF_ASM_OP1(jecxz, 0x67e3, 0, 0, OPT_DISP8)
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/* float */
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/* specific fcomp handling */
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