236 lines
6.1 KiB
C
236 lines
6.1 KiB
C
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/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/debug.h>
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#include <drivers/arm/cci.h>
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#include <drivers/arm/ccn.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/arm/sp804_delay_timer.h>
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#include <drivers/generic_delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/smccc.h>
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#include <lib/xlat_tables/xlat_tables_compat.h>
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#include <services/arm_arch_svc.h>
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#include "fvp_r_private.h"
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#include <plat/arm/common/arm_config.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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/* Defines for GIC Driver build time selection */
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#define FVP_R_GICV3 2
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/*******************************************************************************
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* arm_config holds the characteristics of the differences between the FVP_R
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* platforms. It will be populated during cold boot at each boot stage by the
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* primary before enabling the MPU (to allow interconnect configuration) &
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* used thereafter. Each BL will have its own copy to allow independent
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* operation.
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******************************************************************************/
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arm_config_t arm_config;
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#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
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DEVICE0_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
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DEVICE1_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/*
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* Need to be mapped with write permissions in order to set a new non-volatile
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* counter value.
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*/
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#define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \
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DEVICE2_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/*
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* Table of memory regions for various BL stages to map using the MPU.
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* This doesn't include Trusted SRAM as setup_page_tables() already takes care
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* of mapping it.
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*
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* The flash needs to be mapped as writable in order to erase the FIP's Table of
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* Contents in case of unrecoverable error (see plat_error_handler()).
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*/
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#ifdef IMAGE_BL1
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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V2M_MAP_FLASH0_RW,
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V2M_MAP_IOFPGA,
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MAP_DEVICE0,
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MAP_DEVICE1,
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#if TRUSTED_BOARD_BOOT
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/* To access the Root of Trust Public Key registers. */
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MAP_DEVICE2,
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/* Map DRAM to authenticate NS_BL2U image. */
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ARM_MAP_NS_DRAM1,
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#endif
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{0}
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};
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#endif
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ARM_CASSERT_MMAP
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#if FVP_R_INTERCONNECT_DRIVER != FVP_R_CCN
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static const int fvp_cci400_map[] = {
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PLAT_FVP_R_CCI400_CLUS0_SL_PORT,
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PLAT_FVP_R_CCI400_CLUS1_SL_PORT,
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};
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static const int fvp_cci5xx_map[] = {
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PLAT_FVP_R_CCI5XX_CLUS0_SL_PORT,
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PLAT_FVP_R_CCI5XX_CLUS1_SL_PORT,
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};
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static unsigned int get_interconnect_master(void)
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{
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unsigned int master;
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u_register_t mpidr;
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mpidr = read_mpidr_el1();
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master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ?
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MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr);
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assert(master < FVP_R_CLUSTER_COUNT);
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return master;
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}
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#endif
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/*******************************************************************************
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* Initialize the platform config for future decision making
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******************************************************************************/
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void __init fvp_config_setup(void)
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{
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arm_config.flags |= ARM_CONFIG_BASE_MMAP;
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/*
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* We assume that the presence of MT bit, and therefore shifted
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* affinities, is uniform across the platform: either all CPUs, or no
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* CPUs implement it.
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*/
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if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U) {
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arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF;
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}
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}
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void __init fvp_interconnect_init(void)
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{
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#if FVP_R_INTERCONNECT_DRIVER == FVP_R_CCN
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if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) {
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ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported");
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panic();
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}
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plat_arm_interconnect_init();
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#else
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uintptr_t cci_base = 0U;
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const int *cci_map = NULL;
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unsigned int map_size = 0U;
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/* Initialize the right interconnect */
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if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) {
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cci_base = PLAT_FVP_R_CCI5XX_BASE;
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cci_map = fvp_cci5xx_map;
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map_size = ARRAY_SIZE(fvp_cci5xx_map);
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} else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) {
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cci_base = PLAT_FVP_R_CCI400_BASE;
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cci_map = fvp_cci400_map;
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map_size = ARRAY_SIZE(fvp_cci400_map);
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} else {
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return;
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}
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assert(cci_base != 0U);
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assert(cci_map != NULL);
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cci_init(cci_base, cci_map, map_size);
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#endif
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}
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void fvp_interconnect_enable(void)
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{
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#if FVP_R_INTERCONNECT_DRIVER == FVP_R_CCN
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plat_arm_interconnect_enter_coherency();
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#else
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unsigned int master;
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if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
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ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
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master = get_interconnect_master();
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cci_enable_snoop_dvm_reqs(master);
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}
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#endif
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}
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void fvp_interconnect_disable(void)
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{
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#if FVP_R_INTERCONNECT_DRIVER == FVP_R_CCN
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plat_arm_interconnect_exit_coherency();
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#else
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unsigned int master;
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if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
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ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
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master = get_interconnect_master();
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cci_disable_snoop_dvm_reqs(master);
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}
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#endif
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}
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#if TRUSTED_BOARD_BOOT
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int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
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{
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assert(heap_addr != NULL);
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assert(heap_size != NULL);
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return arm_get_mbedtls_heap(heap_addr, heap_size);
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}
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#endif
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void fvp_timer_init(void)
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{
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#if USE_SP804_TIMER
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/* Enable the clock override for SP804 timer 0, which means that no
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* clock dividers are applied and the raw (35MHz) clock will be used.
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*/
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mmio_write_32(V2M_SP810_BASE, FVP_R_SP810_CTRL_TIM0_OV);
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/* Initialize delay timer driver using SP804 dual timer 0 */
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sp804_timer_init(V2M_SP804_TIMER0_BASE,
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SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV);
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#else
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generic_delay_timer_init();
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/* Enable System level generic timer */
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mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
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CNTCR_FCREQ(0U) | CNTCR_EN);
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#endif /* USE_SP804_TIMER */
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}
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/* Get SOC version */
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int32_t plat_get_soc_version(void)
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{
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return (int32_t)
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((ARM_SOC_IDENTIFICATION_CODE << ARM_SOC_IDENTIFICATION_SHIFT)
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| (ARM_SOC_CONTINUATION_CODE << ARM_SOC_CONTINUATION_SHIFT)
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| FVP_R_SOC_ID);
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}
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/* Get SOC revision */
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int32_t plat_get_soc_revision(void)
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{
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unsigned int sys_id;
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sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
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return (int32_t)((sys_id >> V2M_SYS_ID_REV_SHIFT) &
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V2M_SYS_ID_REV_MASK);
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}
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