fvp_r: initial platform port for fvp_r
Creating a platform port for FVP_R based on the FVP platform. Differences including only-BL1, aarch64, Secure only, and EL2 being the ELmax (No EL3). Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I1283e033fbd4e03c397d0a2c10c4139548b4eee4
This commit is contained in:
laurenw-arm
Manish Pandey
parent
890ee3e87a
commit
03b201c0fb
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -59,7 +59,12 @@
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#define ARM_DRAM_ID 2
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/* The first 4KB of Trusted SRAM are used as shared memory */
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#ifdef __PLAT_ARM_TRUSTED_SRAM_BASE__
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#define ARM_TRUSTED_SRAM_BASE PLAT_ARM_TRUSTED_SRAM_BASE
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#else
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#define ARM_TRUSTED_SRAM_BASE UL(0x04000000)
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#endif /* __PLAT_ARM_TRUSTED_SRAM_BASE__ */
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#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE
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#define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */
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@ -149,8 +154,12 @@
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ARM_TZC_DRAM1_SIZE)
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#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
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ARM_NS_DRAM1_SIZE - 1U)
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#ifdef __PLAT_ARM_DRAM1_BASE__
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#define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE
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#else
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#define ARM_DRAM1_BASE ULL(0x80000000)
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#endif /* __PLAT_ARM_DRAM1_BASE__ */
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#define ARM_DRAM1_SIZE ULL(0x80000000)
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#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
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ARM_DRAM1_SIZE - 1U)
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@ -0,0 +1,67 @@
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/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <bl1/bl1.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <drivers/arm/sp805.h>
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#include "fvp_r_private.h"
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#include <plat/arm/common/arm_config.h>
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#include <plat/arm/common/arm_def.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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/*******************************************************************************
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* Perform any BL1 specific platform actions.
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******************************************************************************/
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void bl1_early_platform_setup(void)
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{
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arm_bl1_early_platform_setup();
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/* Initialize the platform config for future decision making */
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fvp_config_setup();
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/*
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* Initialize Interconnect for this cluster during cold boot.
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* No need for locks as no other CPU is active.
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*/
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fvp_interconnect_init();
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/*
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* Enable coherency in Interconnect for the primary CPU's cluster.
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*/
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fvp_interconnect_enable();
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}
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void plat_arm_secure_wdt_start(void)
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{
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sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL);
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}
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void plat_arm_secure_wdt_stop(void)
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{
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sp805_stop(ARM_SP805_TWDG_BASE);
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}
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void bl1_platform_setup(void)
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{
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arm_bl1_platform_setup();
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/* Initialize System level generic or SP804 timer */
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fvp_timer_init();
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}
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__dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved)
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{
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/* Setup the watchdog to reset the system as soon as possible */
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sp805_refresh(ARM_SP805_TWDG_BASE, 1U);
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while (true) {
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wfi();
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}
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}
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@ -0,0 +1,235 @@
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/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/debug.h>
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#include <drivers/arm/cci.h>
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#include <drivers/arm/ccn.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/arm/sp804_delay_timer.h>
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#include <drivers/generic_delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/smccc.h>
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#include <lib/xlat_tables/xlat_tables_compat.h>
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#include <services/arm_arch_svc.h>
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#include "fvp_r_private.h"
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#include <plat/arm/common/arm_config.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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/* Defines for GIC Driver build time selection */
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#define FVP_R_GICV3 2
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/*******************************************************************************
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* arm_config holds the characteristics of the differences between the FVP_R
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* platforms. It will be populated during cold boot at each boot stage by the
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* primary before enabling the MPU (to allow interconnect configuration) &
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* used thereafter. Each BL will have its own copy to allow independent
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* operation.
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******************************************************************************/
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arm_config_t arm_config;
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#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
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DEVICE0_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
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DEVICE1_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/*
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* Need to be mapped with write permissions in order to set a new non-volatile
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* counter value.
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*/
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#define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \
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DEVICE2_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/*
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* Table of memory regions for various BL stages to map using the MPU.
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* This doesn't include Trusted SRAM as setup_page_tables() already takes care
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* of mapping it.
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*
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* The flash needs to be mapped as writable in order to erase the FIP's Table of
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* Contents in case of unrecoverable error (see plat_error_handler()).
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*/
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#ifdef IMAGE_BL1
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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V2M_MAP_FLASH0_RW,
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V2M_MAP_IOFPGA,
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MAP_DEVICE0,
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MAP_DEVICE1,
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#if TRUSTED_BOARD_BOOT
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/* To access the Root of Trust Public Key registers. */
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MAP_DEVICE2,
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/* Map DRAM to authenticate NS_BL2U image. */
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ARM_MAP_NS_DRAM1,
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#endif
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{0}
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};
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#endif
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ARM_CASSERT_MMAP
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#if FVP_R_INTERCONNECT_DRIVER != FVP_R_CCN
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static const int fvp_cci400_map[] = {
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PLAT_FVP_R_CCI400_CLUS0_SL_PORT,
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PLAT_FVP_R_CCI400_CLUS1_SL_PORT,
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};
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static const int fvp_cci5xx_map[] = {
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PLAT_FVP_R_CCI5XX_CLUS0_SL_PORT,
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PLAT_FVP_R_CCI5XX_CLUS1_SL_PORT,
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};
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static unsigned int get_interconnect_master(void)
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{
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unsigned int master;
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u_register_t mpidr;
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mpidr = read_mpidr_el1();
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master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ?
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MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr);
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assert(master < FVP_R_CLUSTER_COUNT);
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return master;
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}
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#endif
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/*******************************************************************************
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* Initialize the platform config for future decision making
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******************************************************************************/
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void __init fvp_config_setup(void)
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{
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arm_config.flags |= ARM_CONFIG_BASE_MMAP;
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/*
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* We assume that the presence of MT bit, and therefore shifted
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* affinities, is uniform across the platform: either all CPUs, or no
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* CPUs implement it.
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*/
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if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U) {
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arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF;
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}
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}
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void __init fvp_interconnect_init(void)
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{
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#if FVP_R_INTERCONNECT_DRIVER == FVP_R_CCN
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if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) {
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ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported");
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panic();
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}
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plat_arm_interconnect_init();
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#else
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uintptr_t cci_base = 0U;
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const int *cci_map = NULL;
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unsigned int map_size = 0U;
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/* Initialize the right interconnect */
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if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) {
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cci_base = PLAT_FVP_R_CCI5XX_BASE;
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cci_map = fvp_cci5xx_map;
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map_size = ARRAY_SIZE(fvp_cci5xx_map);
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} else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) {
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cci_base = PLAT_FVP_R_CCI400_BASE;
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cci_map = fvp_cci400_map;
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map_size = ARRAY_SIZE(fvp_cci400_map);
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} else {
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return;
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}
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assert(cci_base != 0U);
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assert(cci_map != NULL);
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cci_init(cci_base, cci_map, map_size);
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#endif
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}
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void fvp_interconnect_enable(void)
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{
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#if FVP_R_INTERCONNECT_DRIVER == FVP_R_CCN
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plat_arm_interconnect_enter_coherency();
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#else
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unsigned int master;
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if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
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ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
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master = get_interconnect_master();
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cci_enable_snoop_dvm_reqs(master);
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}
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#endif
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}
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void fvp_interconnect_disable(void)
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{
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#if FVP_R_INTERCONNECT_DRIVER == FVP_R_CCN
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plat_arm_interconnect_exit_coherency();
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#else
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unsigned int master;
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if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
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ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
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master = get_interconnect_master();
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cci_disable_snoop_dvm_reqs(master);
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}
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#endif
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}
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#if TRUSTED_BOARD_BOOT
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int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
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{
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assert(heap_addr != NULL);
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assert(heap_size != NULL);
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return arm_get_mbedtls_heap(heap_addr, heap_size);
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}
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#endif
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void fvp_timer_init(void)
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{
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#if USE_SP804_TIMER
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/* Enable the clock override for SP804 timer 0, which means that no
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* clock dividers are applied and the raw (35MHz) clock will be used.
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*/
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mmio_write_32(V2M_SP810_BASE, FVP_R_SP810_CTRL_TIM0_OV);
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/* Initialize delay timer driver using SP804 dual timer 0 */
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sp804_timer_init(V2M_SP804_TIMER0_BASE,
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SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV);
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#else
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generic_delay_timer_init();
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/* Enable System level generic timer */
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mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
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CNTCR_FCREQ(0U) | CNTCR_EN);
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#endif /* USE_SP804_TIMER */
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}
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/* Get SOC version */
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int32_t plat_get_soc_version(void)
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{
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return (int32_t)
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((ARM_SOC_IDENTIFICATION_CODE << ARM_SOC_IDENTIFICATION_SHIFT)
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| (ARM_SOC_CONTINUATION_CODE << ARM_SOC_CONTINUATION_SHIFT)
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| FVP_R_SOC_ID);
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}
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/* Get SOC revision */
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int32_t plat_get_soc_revision(void)
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{
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unsigned int sys_id;
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sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
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return (int32_t)((sys_id >> V2M_SYS_ID_REV_SHIFT) &
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V2M_SYS_ID_REV_MASK);
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}
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/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef FVP_R_DEF_H
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#define FVP_R_DEF_H
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#include <lib/utils_def.h>
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#ifndef FVP_R_CLUSTER_COUNT
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#error "FVP_R_CLUSTER_COUNT is not set in makefile"
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#endif
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#ifndef FVP_R_MAX_CPUS_PER_CLUSTER
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#error "FVP_R_MAX_CPUS_PER_CLUSTER is not set in makefile"
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#endif
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#ifndef FVP_R_MAX_PE_PER_CPU
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#error "FVP_R_MAX_PE_PER_CPU is not set in makefile"
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#endif
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#define FVP_R_PRIMARY_CPU 0x0
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/* Defines for the Interconnect build selection */
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#define FVP_R_CCI 1
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#define FVP_R_CCN 2
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/******************************************************************************
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* Definition of platform soc id
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*****************************************************************************/
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#define FVP_R_SOC_ID 0
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/*******************************************************************************
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* FVP_R memory map related constants
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******************************************************************************/
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#define FLASH1_BASE UL(0x0c000000)
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#define FLASH1_SIZE UL(0x04000000)
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#define PSRAM_BASE UL(0x14000000)
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#define PSRAM_SIZE UL(0x04000000)
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#define VRAM_BASE UL(0x18000000)
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#define VRAM_SIZE UL(0x02000000)
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/* Aggregate of all devices in the first GB */
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#define DEVICE0_BASE UL(0x20000000)
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#define DEVICE0_SIZE UL(0x0c200000)
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/*
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* In case of FVP_R models with CCN, the CCN register space overlaps into
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* the NSRAM area.
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*/
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#define DEVICE1_BASE UL(0x2e000000)
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#define DEVICE1_SIZE UL(0x1A00000)
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#define NSRAM_BASE UL(0x2e000000)
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#define NSRAM_SIZE UL(0x10000)
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/* Devices in the second GB */
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#define DEVICE2_BASE UL(0x7fe00000)
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#define DEVICE2_SIZE UL(0x00200000)
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/* Non-volatile counters */
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#define TRUSTED_NVCTR_BASE UL(0x7fe70000)
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#define TFW_NVCTR_BASE (TRUSTED_NVCTR_BASE + UL(0x0000))
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#define TFW_NVCTR_SIZE UL(4)
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#define NTFW_CTR_BASE (TRUSTED_NVCTR_BASE + UL(0x0004))
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#define NTFW_CTR_SIZE UL(4)
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/* Keys */
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#define SOC_KEYS_BASE UL(0x7fe80000)
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#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + UL(0x0000))
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#define TZ_PUB_KEY_HASH_SIZE UL(32)
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#define HU_KEY_BASE (SOC_KEYS_BASE + UL(0x0020))
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#define HU_KEY_SIZE UL(16)
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#define END_KEY_BASE (SOC_KEYS_BASE + UL(0x0044))
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#define END_KEY_SIZE UL(32)
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/* Constants to distinguish FVP_R type */
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#define HBI_BASE_FVP_R U(0x020)
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#define REV_BASE_FVP_R_V0 U(0x0)
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#define REV_BASE_FVP_R_REVC U(0x2)
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#define HBI_FOUNDATION_FVP_R U(0x010)
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#define REV_FOUNDATION_FVP_R_V2_0 U(0x0)
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#define REV_FOUNDATION_FVP_R_V2_1 U(0x1)
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#define REV_FOUNDATION_FVP_R_v9_1 U(0x2)
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#define REV_FOUNDATION_FVP_R_v9_6 U(0x3)
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#define BLD_GIC_VE_MMAP U(0x0)
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#define BLD_GIC_A53A57_MMAP U(0x1)
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#define ARCH_MODEL U(0x1)
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/* FVP_R Power controller base address*/
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#define PWRC_BASE UL(0x1c100000)
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/* FVP_R SP804 timer frequency is 35 MHz*/
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#define SP804_TIMER_CLKMULT 1
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#define SP804_TIMER_CLKDIV 35
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/* SP810 controller. FVP_R specific flags */
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#define FVP_R_SP810_CTRL_TIM0_OV BIT_32(16)
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#define FVP_R_SP810_CTRL_TIM1_OV BIT_32(18)
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#define FVP_R_SP810_CTRL_TIM2_OV BIT_32(20)
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||||
#define FVP_R_SP810_CTRL_TIM3_OV BIT_32(22)
|
||||
|
||||
#endif /* FVP_R_DEF_H */
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Copyright (c) 2021, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <drivers/arm/sp805.h>
|
||||
#include <drivers/cfi/v2m_flash.h>
|
||||
#include <plat/arm/common/plat_arm.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
/*
|
||||
* FVP_R error handler
|
||||
*/
|
||||
__dead2 void plat_arm_error_handler(int err)
|
||||
{
|
||||
int ret;
|
||||
|
||||
switch (err) {
|
||||
case -ENOENT:
|
||||
case -EAUTH:
|
||||
/* Image load or authentication error. Erase the ToC */
|
||||
INFO("Erasing FIP ToC from flash...\n");
|
||||
(void)nor_unlock(PLAT_ARM_FIP_BASE);
|
||||
ret = nor_word_program(PLAT_ARM_FIP_BASE, 0);
|
||||
if (ret != 0) {
|
||||
ERROR("Cannot erase ToC\n");
|
||||
} else {
|
||||
INFO("Done\n");
|
||||
}
|
||||
break;
|
||||
default:
|
||||
/* Unexpected error */
|
||||
break;
|
||||
}
|
||||
|
||||
(void)console_flush();
|
||||
|
||||
/* Setup the watchdog to reset the system as soon as possible */
|
||||
sp805_refresh(ARM_SP805_TWDG_BASE, 1U);
|
||||
|
||||
while (true) {
|
||||
wfi();
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,166 @@
|
|||
/*
|
||||
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
#include <drivers/arm/fvp/fvp_pwrc.h>
|
||||
#include <drivers/arm/gicv2.h>
|
||||
#include <drivers/arm/gicv3.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
|
||||
.globl plat_secondary_cold_boot_setup
|
||||
.globl plat_get_my_entrypoint
|
||||
.globl plat_is_my_cpu_primary
|
||||
.globl plat_arm_calc_core_pos
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* void plat_secondary_cold_boot_setup (void);
|
||||
*
|
||||
* This function performs any platform specific actions
|
||||
* needed for a secondary cpu after a cold reset e.g
|
||||
* mark the cpu's presence, mechanism to place it in a
|
||||
* holding pen etc.
|
||||
* TODO: Should we read the PSYS register to make sure
|
||||
* that the request has gone through.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
func plat_secondary_cold_boot_setup
|
||||
/* ---------------------------------------------
|
||||
* Power down this cpu.
|
||||
* TODO: Do we need to worry about powering the
|
||||
* cluster down as well here? That will need
|
||||
* locks which we won't have unless an elf-
|
||||
* loader zeroes out the zi section.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
mrs x0, mpidr_el1
|
||||
mov_imm x1, PWRC_BASE
|
||||
str w0, [x1, #PPOFFR_OFF]
|
||||
|
||||
/* ---------------------------------------------
|
||||
* There is no sane reason to come out of this
|
||||
* wfi so panic if we do. This cpu will be pow-
|
||||
* ered on and reset by the cpu_on pm api
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
dsb sy
|
||||
wfi
|
||||
no_ret plat_panic_handler
|
||||
endfunc plat_secondary_cold_boot_setup
|
||||
|
||||
/* ---------------------------------------------------------------------
|
||||
* uintptr_t plat_get_my_entrypoint (void);
|
||||
*
|
||||
* Main job of this routine is to distinguish between a cold and warm
|
||||
* boot. On FVP_R, this information can be queried from the power
|
||||
* controller. The Power Control SYS Status Register (PSYSR) indicates
|
||||
* the wake-up reason for the CPU.
|
||||
*
|
||||
* For a cold boot, return 0.
|
||||
* For a warm boot, read the mailbox and return the address it contains.
|
||||
*
|
||||
* TODO: PSYSR is a common register and should be
|
||||
* accessed using locks. Since it is not possible
|
||||
* to use locks immediately after a cold reset
|
||||
* we are relying on the fact that after a cold
|
||||
* reset all cpus will read the same WK field
|
||||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
func plat_get_my_entrypoint
|
||||
/* ---------------------------------------------------------------------
|
||||
* When bit PSYSR.WK indicates either "Wake by PPONR" or "Wake by GIC
|
||||
* WakeRequest signal" then it is a warm boot.
|
||||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
mrs x2, mpidr_el1
|
||||
mov_imm x1, PWRC_BASE
|
||||
str w2, [x1, #PSYSR_OFF]
|
||||
ldr w2, [x1, #PSYSR_OFF]
|
||||
ubfx w2, w2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH
|
||||
cmp w2, #WKUP_PPONR
|
||||
beq warm_reset
|
||||
cmp w2, #WKUP_GICREQ
|
||||
beq warm_reset
|
||||
|
||||
/* Cold reset */
|
||||
mov x0, #0
|
||||
ret
|
||||
|
||||
warm_reset:
|
||||
/* ---------------------------------------------------------------------
|
||||
* A mailbox is maintained in the trusted SRAM. It is flushed out of the
|
||||
* caches after every update using normal memory so it is safe to read
|
||||
* it here with SO attributes.
|
||||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
|
||||
ldr x0, [x0]
|
||||
cbz x0, _panic_handler
|
||||
ret
|
||||
|
||||
/* ---------------------------------------------------------------------
|
||||
* The power controller indicates this is a warm reset but the mailbox
|
||||
* is empty. This should never happen!
|
||||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
_panic_handler:
|
||||
no_ret plat_panic_handler
|
||||
endfunc plat_get_my_entrypoint
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* unsigned int plat_is_my_cpu_primary (void);
|
||||
*
|
||||
* Find out whether the current cpu is the primary
|
||||
* cpu.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
func plat_is_my_cpu_primary
|
||||
mrs x0, mpidr_el1
|
||||
mov_imm x1, MPIDR_AFFINITY_MASK
|
||||
and x0, x0, x1
|
||||
cmp x0, #FVP_R_PRIMARY_CPU
|
||||
cset w0, eq
|
||||
ret
|
||||
endfunc plat_is_my_cpu_primary
|
||||
|
||||
/* ---------------------------------------------------------------------
|
||||
* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
|
||||
*
|
||||
* Function to calculate the core position on FVP_R.
|
||||
*
|
||||
* (ClusterId * FVP_R_MAX_CPUS_PER_CLUSTER * FVP_R_MAX_PE_PER_CPU) +
|
||||
* (CPUId * FVP_R_MAX_PE_PER_CPU) +
|
||||
* ThreadId
|
||||
*
|
||||
* which can be simplified as:
|
||||
*
|
||||
* ((ClusterId * FVP_R_MAX_CPUS_PER_CLUSTER + CPUId) * FVP_R_MAX_PE_PER_CPU)
|
||||
* + ThreadId
|
||||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
func plat_arm_calc_core_pos
|
||||
/*
|
||||
* Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it
|
||||
* look as if in a multi-threaded implementation.
|
||||
*/
|
||||
tst x0, #MPIDR_MT_MASK
|
||||
lsl x3, x0, #MPIDR_AFFINITY_BITS
|
||||
csel x3, x3, x0, eq
|
||||
|
||||
/* Extract individual affinity fields from MPIDR */
|
||||
ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
|
||||
ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
|
||||
ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
|
||||
|
||||
/* Compute linear position */
|
||||
mov x4, #FVP_R_MAX_CPUS_PER_CLUSTER
|
||||
madd x1, x2, x4, x1
|
||||
mov x5, #FVP_R_MAX_PE_PER_CPU
|
||||
madd x0, x1, x5, x0
|
||||
ret
|
||||
endfunc plat_arm_calc_core_pos
|
||||
|
|
@ -0,0 +1,115 @@
|
|||
/*
|
||||
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <drivers/io/io_driver.h>
|
||||
#include <drivers/io/io_semihosting.h>
|
||||
#include <drivers/io/io_storage.h>
|
||||
#include <lib/semihosting.h>
|
||||
#include <plat/arm/common/plat_arm.h>
|
||||
#include <plat/common/common_def.h>
|
||||
|
||||
/* Semihosting filenames */
|
||||
#define TB_FW_CONFIG_NAME "fvp_tb_fw_config.dtb"
|
||||
#define HW_CONFIG_NAME "hw_config.dtb"
|
||||
|
||||
#if TRUSTED_BOARD_BOOT
|
||||
#define TRUSTED_BOOT_FW_CERT_NAME "tb_fw.crt"
|
||||
#define TRUSTED_KEY_CERT_NAME "trusted_key.crt"
|
||||
#define SOC_FW_KEY_CERT_NAME "soc_fw_key.crt"
|
||||
#define TOS_FW_KEY_CERT_NAME "tos_fw_key.crt"
|
||||
#define NT_FW_KEY_CERT_NAME "nt_fw_key.crt"
|
||||
#define SOC_FW_CONTENT_CERT_NAME "soc_fw_content.crt"
|
||||
#define TOS_FW_CONTENT_CERT_NAME "tos_fw_content.crt"
|
||||
#define NT_FW_CONTENT_CERT_NAME "nt_fw_content.crt"
|
||||
#endif /* TRUSTED_BOARD_BOOT */
|
||||
|
||||
/* IO devices */
|
||||
static const io_dev_connector_t *sh_dev_con;
|
||||
static uintptr_t sh_dev_handle;
|
||||
|
||||
static const io_file_spec_t sh_file_spec[] = {
|
||||
[TB_FW_CONFIG_ID] = {
|
||||
.path = TB_FW_CONFIG_NAME,
|
||||
.mode = FOPEN_MODE_RB
|
||||
},
|
||||
[HW_CONFIG_ID] = {
|
||||
.path = HW_CONFIG_NAME,
|
||||
.mode = FOPEN_MODE_RB
|
||||
},
|
||||
#if TRUSTED_BOARD_BOOT
|
||||
[TRUSTED_KEY_CERT_ID] = {
|
||||
.path = TRUSTED_KEY_CERT_NAME,
|
||||
.mode = FOPEN_MODE_RB
|
||||
},
|
||||
[NON_TRUSTED_FW_KEY_CERT_ID] = {
|
||||
.path = NT_FW_KEY_CERT_NAME,
|
||||
.mode = FOPEN_MODE_RB
|
||||
},
|
||||
[NON_TRUSTED_FW_CONTENT_CERT_ID] = {
|
||||
.path = NT_FW_CONTENT_CERT_NAME,
|
||||
.mode = FOPEN_MODE_RB
|
||||
},
|
||||
#endif /* TRUSTED_BOARD_BOOT */
|
||||
};
|
||||
|
||||
|
||||
static int open_semihosting(const uintptr_t spec)
|
||||
{
|
||||
int result;
|
||||
uintptr_t local_image_handle;
|
||||
|
||||
/* See if the file exists on semi-hosting.*/
|
||||
result = io_dev_init(sh_dev_handle, (uintptr_t)NULL);
|
||||
if (result == 0) {
|
||||
result = io_open(sh_dev_handle, spec, &local_image_handle);
|
||||
if (result == 0) {
|
||||
VERBOSE("Using Semi-hosting IO\n");
|
||||
io_close(local_image_handle);
|
||||
}
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
void plat_arm_io_setup(void)
|
||||
{
|
||||
int io_result;
|
||||
|
||||
io_result = arm_io_setup();
|
||||
if (io_result < 0) {
|
||||
panic();
|
||||
}
|
||||
|
||||
/* Register the additional IO devices on this platform */
|
||||
io_result = register_io_dev_sh(&sh_dev_con);
|
||||
if (io_result < 0) {
|
||||
panic();
|
||||
}
|
||||
|
||||
/* Open connections to devices and cache the handles */
|
||||
io_result = io_dev_open(sh_dev_con, (uintptr_t)NULL, &sh_dev_handle);
|
||||
if (io_result < 0) {
|
||||
panic();
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* FVP_R provides semihosting as an alternative to load images
|
||||
*/
|
||||
int plat_arm_get_alt_image_source(unsigned int image_id, uintptr_t *dev_handle,
|
||||
uintptr_t *image_spec)
|
||||
{
|
||||
int result = open_semihosting((const uintptr_t)&sh_file_spec[image_id]);
|
||||
|
||||
if (result == 0) {
|
||||
*dev_handle = sh_dev_handle;
|
||||
*image_spec = (uintptr_t)&sh_file_spec[image_id];
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef FVP_R_PRIVATE_H
|
||||
#define FVP_R_PRIVATE_H
|
||||
|
||||
#include <plat/arm/common/plat_arm.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Function and variable prototypes
|
||||
******************************************************************************/
|
||||
|
||||
void fvp_config_setup(void);
|
||||
|
||||
void fvp_interconnect_init(void);
|
||||
void fvp_interconnect_enable(void);
|
||||
void fvp_interconnect_disable(void);
|
||||
void fvp_timer_init(void);
|
||||
|
||||
#endif /* FVP_R_PRIVATE_H */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
#define RANDOM_CANARY_VALUE ((u_register_t) 8092347823957523895ULL)
|
||||
|
||||
u_register_t plat_get_stack_protector_canary(void)
|
||||
{
|
||||
/*
|
||||
* Ideally, a random number should be returned instead of the
|
||||
* combination of a timer's value and a compile-time constant. As the
|
||||
* FVP_R does not have any random number generator, this is better than
|
||||
* nothing but not necessarily really secure.
|
||||
*/
|
||||
return RANDOM_CANARY_VALUE ^ read_cntpct_el0();
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
#include <lib/fconf/fconf.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <tools_share/tbbr_oid.h>
|
||||
|
||||
#include <plat/arm/common/fconf_nv_cntr_getter.h>
|
||||
#include <plat/arm/common/plat_arm.h>
|
||||
#include <plat/common/platform.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
|
||||
/*
|
||||
* Return the ROTPK hash in the following ASN.1 structure in DER format:
|
||||
*
|
||||
* AlgorithmIdentifier ::= SEQUENCE {
|
||||
* algorithm OBJECT IDENTIFIER,
|
||||
* parameters ANY DEFINED BY algorithm OPTIONAL
|
||||
* }
|
||||
*
|
||||
* DigestInfo ::= SEQUENCE {
|
||||
* digestAlgorithm AlgorithmIdentifier,
|
||||
* digest OCTET STRING
|
||||
* }
|
||||
*/
|
||||
int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
|
||||
unsigned int *flags)
|
||||
{
|
||||
return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
|
||||
}
|
||||
|
||||
/*
|
||||
* Store a new non-volatile counter value.
|
||||
*
|
||||
* On some FVP_R versions, the non-volatile counters are read-only so this
|
||||
* function will always fail.
|
||||
*
|
||||
* Return: 0 = success, Otherwise = error
|
||||
*/
|
||||
int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr)
|
||||
{
|
||||
const char *oid;
|
||||
uintptr_t nv_ctr_addr;
|
||||
|
||||
assert(cookie != NULL);
|
||||
|
||||
oid = (const char *)cookie;
|
||||
if (strcmp(oid, TRUSTED_FW_NVCOUNTER_OID) == 0) {
|
||||
nv_ctr_addr = FCONF_GET_PROPERTY(cot, nv_cntr_addr,
|
||||
TRUSTED_NV_CTR_ID);
|
||||
} else if (strcmp(oid, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) {
|
||||
nv_ctr_addr = FCONF_GET_PROPERTY(cot, nv_cntr_addr,
|
||||
NON_TRUSTED_NV_CTR_ID);
|
||||
} else {
|
||||
return 1;
|
||||
}
|
||||
|
||||
mmio_write_32(nv_ctr_addr, nv_ctr);
|
||||
|
||||
/*
|
||||
* If the FVP_R models a locked counter then its value cannot be updated
|
||||
* and the above write operation has been silently ignored.
|
||||
*/
|
||||
return (mmio_read_32(nv_ctr_addr) == nv_ctr) ? 0 : 1;
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/*
|
||||
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef PLAT_LD_S
|
||||
#define PLAT_LD_S
|
||||
|
||||
#include <plat/arm/common/arm_tzc_dram.ld.S>
|
||||
|
||||
#endif /* PLAT_LD_S */
|
||||
|
|
@ -0,0 +1,242 @@
|
|||
/*
|
||||
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLATFORM_DEF_H
|
||||
#define PLATFORM_DEF_H
|
||||
|
||||
#include "../fvp_r_def.h"
|
||||
#include <drivers/arm/tzc400.h>
|
||||
#include <lib/utils_def.h>
|
||||
#include <plat/arm/board/common/v2m_def.h>
|
||||
|
||||
#include <plat/arm/common/arm_def.h>
|
||||
#include <plat/common/common_def.h>
|
||||
|
||||
|
||||
#define NO_EL3 1
|
||||
|
||||
/* Required platform porting definitions */
|
||||
#define PLATFORM_CORE_COUNT (U(FVP_R_CLUSTER_COUNT) * \
|
||||
U(FVP_R_MAX_CPUS_PER_CLUSTER) * \
|
||||
U(FVP_R_MAX_PE_PER_CPU))
|
||||
|
||||
#define PLAT_NUM_PWR_DOMAINS (U(FVP_R_CLUSTER_COUNT) + \
|
||||
PLATFORM_CORE_COUNT + U(1))
|
||||
|
||||
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2
|
||||
|
||||
/*
|
||||
* Other platform porting definitions are provided by included headers
|
||||
*/
|
||||
|
||||
/*
|
||||
* Required ARM standard platform porting definitions
|
||||
*/
|
||||
#define PLAT_ARM_CLUSTER_COUNT U(FVP_R_CLUSTER_COUNT)
|
||||
|
||||
#define PLAT_ARM_DRAM1_BASE ULL(0x0)
|
||||
|
||||
#define PLAT_ARM_TRUSTED_ROM_BASE UL(0x80000000)
|
||||
#define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */
|
||||
|
||||
#define PLAT_ARM_TRUSTED_SRAM_BASE UL(0x84000000)
|
||||
#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */
|
||||
|
||||
#define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x86000000)
|
||||
#define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */
|
||||
|
||||
/* virtual address used by dynamic mem_protect for chunk_base */
|
||||
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
|
||||
|
||||
/* No SCP in FVP_R */
|
||||
#define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0)
|
||||
|
||||
#define PLAT_ARM_DRAM2_BASE ULL(0x080000000)
|
||||
#define PLAT_ARM_DRAM2_SIZE UL(0x80000000)
|
||||
|
||||
#define PLAT_HW_CONFIG_DTB_BASE ULL(0x12000000)
|
||||
#define PLAT_HW_CONFIG_DTB_SIZE ULL(0x8000)
|
||||
|
||||
#define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \
|
||||
PLAT_HW_CONFIG_DTB_BASE, \
|
||||
PLAT_HW_CONFIG_DTB_SIZE, \
|
||||
MT_MEMORY | MT_RO | MT_NS)
|
||||
/*
|
||||
* Load address of BL33 for this platform port
|
||||
*/
|
||||
#define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000))
|
||||
|
||||
/*
|
||||
* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
|
||||
* plat_arm_mmap array defined for each BL stage.
|
||||
*/
|
||||
#if !USE_ROMLIB
|
||||
# define PLAT_ARM_MMAP_ENTRIES 11
|
||||
# define MAX_XLAT_TABLES 5
|
||||
#else
|
||||
# define PLAT_ARM_MMAP_ENTRIES 12
|
||||
# define MAX_XLAT_TABLES 6
|
||||
#endif
|
||||
|
||||
/*
|
||||
* These nominally reserve the last block of flash for PSCI MEM PROTECT flag,
|
||||
* but no PSCI in FVP_R platform, so reserve nothing:
|
||||
*/
|
||||
#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE
|
||||
#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE 0
|
||||
|
||||
/*
|
||||
* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
|
||||
* plus a little space for growth.
|
||||
*/
|
||||
#define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000)
|
||||
|
||||
/*
|
||||
* PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
|
||||
*/
|
||||
|
||||
#if USE_ROMLIB
|
||||
#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000)
|
||||
#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000)
|
||||
#define FVP_R_BL2_ROMLIB_OPTIMIZATION UL(0x6000)
|
||||
#else
|
||||
#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0)
|
||||
#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0)
|
||||
#define FVP_R_BL2_ROMLIB_OPTIMIZATION UL(0)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
|
||||
* little space for growth.
|
||||
*/
|
||||
#if TRUSTED_BOARD_BOOT
|
||||
#if COT_DESC_IN_DTB
|
||||
# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_R_BL2_ROMLIB_OPTIMIZATION)
|
||||
#else
|
||||
# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_R_BL2_ROMLIB_OPTIMIZATION)
|
||||
#endif
|
||||
#else
|
||||
# define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - FVP_R_BL2_ROMLIB_OPTIMIZATION)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
|
||||
* calculated using the current BL31 PROGBITS debug size plus the sizes of
|
||||
* BL2 and BL1-RW
|
||||
*/
|
||||
#define PLAT_ARM_MAX_BL31_SIZE UL(0x3D000)
|
||||
|
||||
/*
|
||||
* Size of cacheable stacks
|
||||
*/
|
||||
#if defined(IMAGE_BL1)
|
||||
# if TRUSTED_BOARD_BOOT
|
||||
# define PLATFORM_STACK_SIZE UL(0x1000)
|
||||
# else
|
||||
# define PLATFORM_STACK_SIZE UL(0x500)
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#define MAX_IO_DEVICES 3
|
||||
#define MAX_IO_HANDLES 4
|
||||
|
||||
/* Reserve the last block of flash for PSCI MEM PROTECT flag */
|
||||
#define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE
|
||||
#define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
|
||||
|
||||
#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
|
||||
#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
|
||||
|
||||
/*
|
||||
* PL011 related constants
|
||||
*/
|
||||
#define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE
|
||||
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
|
||||
|
||||
#define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE
|
||||
#define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ
|
||||
|
||||
#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
|
||||
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
|
||||
|
||||
#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE
|
||||
#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ
|
||||
|
||||
/* CCI related constants */
|
||||
#define PLAT_FVP_R_CCI400_BASE UL(0xac090000)
|
||||
#define PLAT_FVP_R_CCI400_CLUS0_SL_PORT 3
|
||||
#define PLAT_FVP_R_CCI400_CLUS1_SL_PORT 4
|
||||
|
||||
/* CCI-500/CCI-550 on Base platform */
|
||||
#define PLAT_FVP_R_CCI5XX_BASE UL(0xaa000000)
|
||||
#define PLAT_FVP_R_CCI5XX_CLUS0_SL_PORT 5
|
||||
#define PLAT_FVP_R_CCI5XX_CLUS1_SL_PORT 6
|
||||
|
||||
/* CCN related constants. Only CCN 502 is currently supported */
|
||||
#define PLAT_ARM_CCN_BASE UL(0xae000000)
|
||||
#define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11
|
||||
|
||||
/* System timer related constants */
|
||||
#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
|
||||
|
||||
/* Mailbox base address */
|
||||
#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
|
||||
|
||||
|
||||
/* TrustZone controller related constants
|
||||
*
|
||||
* Currently only filters 0 and 2 are connected on Base FVP_R.
|
||||
* Filter 0 : CPU clusters (no access to DRAM by default)
|
||||
* Filter 1 : not connected
|
||||
* Filter 2 : LCDs (access to VRAM allowed by default)
|
||||
* Filter 3 : not connected
|
||||
* Programming unconnected filters will have no effect at the
|
||||
* moment. These filter could, however, be connected in future.
|
||||
* So care should be taken not to configure the unused filters.
|
||||
*
|
||||
* Allow only non-secure access to all DRAM to supported devices.
|
||||
* Give access to the CPUs and Virtio. Some devices
|
||||
* would normally use the default ID so allow that too.
|
||||
*/
|
||||
#define PLAT_ARM_TZC_BASE UL(0xaa4a0000)
|
||||
#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
|
||||
|
||||
#define PLAT_ARM_TZC_NS_DEV_ACCESS ( \
|
||||
TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_DEFAULT) | \
|
||||
TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_PCI) | \
|
||||
TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_AP) | \
|
||||
TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_VIRTIO) | \
|
||||
TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_VIRTIO_OLD))
|
||||
|
||||
/*
|
||||
* GIC related constants to cater for both GICv2 and GICv3 instances of an
|
||||
* FVP_R. They could be overridden at runtime in case the FVP_R implements the
|
||||
* legacy VE memory map.
|
||||
*/
|
||||
#define PLAT_ARM_GICD_BASE BASE_GICD_BASE
|
||||
#define PLAT_ARM_GICR_BASE BASE_GICR_BASE
|
||||
#define PLAT_ARM_GICC_BASE BASE_GICC_BASE
|
||||
|
||||
#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
|
||||
PLAT_SP_IMAGE_NS_BUF_SIZE)
|
||||
|
||||
#define PLAT_SP_PRI PLAT_RAS_PRI
|
||||
|
||||
/*
|
||||
* Physical and virtual address space limits for MPU in AARCH64 & AARCH32 modes
|
||||
*/
|
||||
#ifdef __aarch64__
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
|
||||
#else
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
|
||||
#endif
|
||||
|
||||
#define ARM_SOC_CONTINUATION_SHIFT U(24)
|
||||
#define ARM_SOC_IDENTIFICATION_SHIFT U(16)
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
#
|
||||
# Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
# Only aarch64 ARCH supported for FVP_R
|
||||
ARCH := aarch64
|
||||
|
||||
# Override to exclude BL2, BL2U, BL31, and BL33 for FVP_R
|
||||
override NEED_BL2 := no
|
||||
override NEED_BL2U := no
|
||||
override NEED_BL31 := no
|
||||
override NEED_BL33 := no
|
||||
|
||||
# Default cluster count for FVP_R
|
||||
FVP_R_CLUSTER_COUNT := 2
|
||||
|
||||
# Default number of CPUs per cluster on FVP_R
|
||||
FVP_R_MAX_CPUS_PER_CLUSTER := 4
|
||||
|
||||
# Default number of threads per CPU on FVP_R
|
||||
FVP_R_MAX_PE_PER_CPU := 1
|
||||
|
||||
# Need to revisit this for FVP_R
|
||||
FVP_R_DT_PREFIX := fvp-base-gicv3-psci
|
||||
|
||||
# Pass FVP_R_CLUSTER_COUNT to the build system.
|
||||
$(eval $(call add_define,FVP_R_CLUSTER_COUNT))
|
||||
|
||||
# Pass FVP_R_MAX_CPUS_PER_CLUSTER to the build system.
|
||||
$(eval $(call add_define,FVP_R_MAX_CPUS_PER_CLUSTER))
|
||||
|
||||
# Pass FVP_R_MAX_PE_PER_CPU to the build system.
|
||||
$(eval $(call add_define,FVP_R_MAX_PE_PER_CPU))
|
||||
|
||||
# Sanity check the cluster count and if FVP_R_CLUSTER_COUNT <= 2,
|
||||
# choose the CCI driver , else the CCN driver
|
||||
ifeq ($(FVP_R_CLUSTER_COUNT), 0)
|
||||
$(error "Incorrect cluster count specified for FVP_R port")
|
||||
else ifeq ($(FVP_R_CLUSTER_COUNT),$(filter $(FVP_R_CLUSTER_COUNT),1 2))
|
||||
FVP_R_INTERCONNECT_DRIVER := FVP_R_CCI
|
||||
else
|
||||
FVP_R_INTERCONNECT_DRIVER := FVP_R_CCN
|
||||
endif
|
||||
|
||||
$(eval $(call add_define,FVP_R_INTERCONNECT_DRIVER))
|
||||
|
||||
ifeq (${FVP_R_INTERCONNECT_DRIVER}, FVP_R_CCI)
|
||||
FVP_R_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c
|
||||
else ifeq (${FVP_R_INTERCONNECT_DRIVER}, FVP_R_CCN)
|
||||
FVP_R_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \
|
||||
plat/arm/common/arm_ccn.c
|
||||
else
|
||||
$(error "Incorrect CCN driver chosen on FVP_R port")
|
||||
endif
|
||||
|
||||
PLAT_INCLUDES := -Iplat/arm/board/fvp_r/include
|
||||
|
||||
PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp_r/fvp_r_common.c
|
||||
|
||||
FVP_R_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
|
||||
|
||||
# select a different set of CPU files, depending on whether we compile for
|
||||
# hardware assisted coherency cores or not
|
||||
ifeq (${HW_ASSISTED_COHERENCY}, 0)
|
||||
# Cores used without DSU
|
||||
# FVP_R_CPU_LIBS += lib/cpus/aarch64/fvp_r.S
|
||||
else
|
||||
# Cores used with DSU only
|
||||
# FVP_R_CPU_LIBS += lib/cpus/aarch64/fvp_r.S
|
||||
endif
|
||||
|
||||
BL1_SOURCES += drivers/arm/sp805/sp805.c \
|
||||
drivers/delay_timer/delay_timer.c \
|
||||
drivers/io/io_semihosting.c \
|
||||
lib/semihosting/semihosting.c \
|
||||
lib/semihosting/${ARCH}/semihosting_call.S \
|
||||
plat/arm/board/fvp_r/fvp_r_helpers.S \
|
||||
plat/arm/board/fvp_r/fvp_r_bl1_setup.c \
|
||||
plat/arm/board/fvp_r/fvp_r_err.c \
|
||||
plat/arm/board/fvp_r/fvp_r_io_storage.c \
|
||||
${FVP_R_CPU_LIBS} \
|
||||
${FVP_R_INTERCONNECT_SOURCES}
|
||||
|
||||
ifeq (${USE_SP804_TIMER},1)
|
||||
BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
|
||||
else
|
||||
BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c
|
||||
endif
|
||||
|
||||
# Enable Activity Monitor Unit extensions by default
|
||||
ENABLE_AMU := 1
|
||||
|
||||
ifneq (${ENABLE_STACK_PROTECTOR},0)
|
||||
PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp_r/fvp_r_stack_protector.c
|
||||
endif
|
||||
|
||||
ifeq (${ARCH},aarch32)
|
||||
NEED_BL32 := yes
|
||||
endif
|
||||
|
||||
ifneq (${BL2_AT_EL3}, 0)
|
||||
override BL1_SOURCES =
|
||||
endif
|
||||
|
||||
# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env)
|
||||
ifdef UNIX_MK
|
||||
FVP_R_HW_CONFIG_DTS := fdts/${FVP_R_DT_PREFIX}.dts
|
||||
FDT_SOURCES += $(addprefix plat/arm/board/fvp_r/fdts/, \
|
||||
${PLAT}_fw_config.dts \
|
||||
${PLAT}_nt_fw_config.dts \
|
||||
)
|
||||
|
||||
FVP_R_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
|
||||
FVP_R_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
|
||||
|
||||
# Add the FW_CONFIG to FIP and specify the same to certtool
|
||||
$(eval $(call TOOL_ADD_PAYLOAD,${FVP_R_FW_CONFIG},--fw-config,${FVP_R_FW_CONFIG}))
|
||||
# Add the NT_FW_CONFIG to FIP and specify the same to certtool
|
||||
$(eval $(call TOOL_ADD_PAYLOAD,${FVP_R_NT_FW_CONFIG},--nt-fw-config,${FVP_R_NT_FW_CONFIG}))
|
||||
|
||||
FDT_SOURCES += ${FVP_R_HW_CONFIG_DTS}
|
||||
$(eval FVP_R_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_R_HW_CONFIG_DTS)))
|
||||
|
||||
# Add the HW_CONFIG to FIP and specify the same to certtool
|
||||
$(eval $(call TOOL_ADD_PAYLOAD,${FVP_R_HW_CONFIG},--hw-config,${FVP_R_HW_CONFIG}))
|
||||
endif
|
||||
|
||||
include plat/arm/board/common/board_common.mk
|
||||
include plat/arm/common/arm_common.mk
|
||||
Loading…
Reference in New Issue