2014-07-17 16:06:39 +01:00
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/*
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2020-08-04 17:13:14 +01:00
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* Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
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2014-07-17 16:06:39 +01:00
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*
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2017-05-03 09:38:09 +01:00
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* SPDX-License-Identifier: BSD-3-Clause
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2014-07-17 16:06:39 +01:00
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*/
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2018-07-20 09:17:26 +01:00
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#ifndef JUNO_DEF_H
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#define JUNO_DEF_H
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2014-07-17 16:06:39 +01:00
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2018-12-14 00:18:21 +00:00
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#include <lib/utils_def.h>
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2014-07-17 16:06:39 +01:00
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2020-08-04 17:13:14 +01:00
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/******************************************************************************
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* Definition of platform soc id
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*****************************************************************************/
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#define JUNO_SOC_ID 1
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2014-07-17 16:06:39 +01:00
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/*******************************************************************************
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* Juno memory map related constants
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******************************************************************************/
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2015-02-04 14:06:10 +00:00
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/* Board revisions */
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2018-10-30 16:12:32 +00:00
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#define REV_JUNO_R0 U(0x1) /* Rev B */
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#define REV_JUNO_R1 U(0x2) /* Rev C */
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#define REV_JUNO_R2 U(0x3) /* Rev D */
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2014-07-17 16:06:39 +01:00
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2015-03-19 19:22:44 +00:00
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/* Bypass offset from start of NOR flash */
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2018-10-30 16:12:32 +00:00
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#define BL1_ROM_BYPASS_OFFSET UL(0x03EC0000)
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2014-07-17 16:06:39 +01:00
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2018-10-30 16:12:32 +00:00
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#define EMMC_BASE UL(0x0c000000)
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#define EMMC_SIZE UL(0x04000000)
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2014-07-17 16:06:39 +01:00
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2018-10-30 16:12:32 +00:00
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#define PSRAM_BASE UL(0x14000000)
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#define PSRAM_SIZE UL(0x02000000)
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2014-07-17 16:06:39 +01:00
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2018-10-30 16:12:32 +00:00
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#define JUNO_SSC_VER_PART_NUM U(0x030)
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2014-07-17 16:06:39 +01:00
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2016-02-01 14:04:34 +00:00
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/*******************************************************************************
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* Juno topology related constants
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******************************************************************************/
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2019-12-13 16:23:18 +00:00
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#define JUNO_CLUSTER_COUNT U(2)
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#define JUNO_CLUSTER0_CORE_COUNT U(2)
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#define JUNO_CLUSTER1_CORE_COUNT U(4)
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2016-02-01 14:04:34 +00:00
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2014-07-17 16:06:39 +01:00
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/*******************************************************************************
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* TZC-400 related constants
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******************************************************************************/
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2015-03-19 19:22:44 +00:00
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#define TZC400_NSAID_CCI400 0 /* Note: Same as default NSAID!! */
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#define TZC400_NSAID_PCIE 1
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#define TZC400_NSAID_HDLCD0 2
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#define TZC400_NSAID_HDLCD1 3
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#define TZC400_NSAID_USB 4
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#define TZC400_NSAID_DMA330 5
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#define TZC400_NSAID_THINLINKS 6
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#define TZC400_NSAID_AP 9
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#define TZC400_NSAID_GPU 10
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#define TZC400_NSAID_SCP 11
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#define TZC400_NSAID_CORESIGHT 12
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2014-08-12 17:24:30 +01:00
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2017-02-27 12:21:43 +00:00
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/*******************************************************************************
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* TRNG related constants
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******************************************************************************/
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2018-10-30 16:12:32 +00:00
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#define TRNG_BASE UL(0x7FE60000)
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2017-02-27 12:21:43 +00:00
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#define TRNG_NOUTPUTS 4
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2018-10-30 16:12:32 +00:00
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#define TRNG_STATUS UL(0x10)
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#define TRNG_INTMASK UL(0x14)
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#define TRNG_CONFIG UL(0x18)
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#define TRNG_CONTROL UL(0x1C)
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2017-02-28 14:43:15 +00:00
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#define TRNG_NBYTES 16 /* Number of bytes generated per round. */
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2017-02-27 12:21:43 +00:00
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2015-01-09 14:30:58 +00:00
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/*******************************************************************************
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* MMU-401 related constants
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******************************************************************************/
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2018-10-30 16:12:32 +00:00
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#define MMU401_SSD_OFFSET UL(0x4000)
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#define MMU401_DMA330_BASE UL(0x7fb00000)
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2015-03-19 19:22:44 +00:00
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2015-06-24 17:51:09 +01:00
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/*******************************************************************************
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* Interrupt handling constants
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******************************************************************************/
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#define JUNO_IRQ_DMA_SMMU 126
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#define JUNO_IRQ_HDLCD0_SMMU 128
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#define JUNO_IRQ_HDLCD1_SMMU 130
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#define JUNO_IRQ_USB_SMMU 132
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#define JUNO_IRQ_THIN_LINKS_SMMU 134
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#define JUNO_IRQ_SEC_I2C 137
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#define JUNO_IRQ_GPU_SMMU_1 73
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#define JUNO_IRQ_ETR_SMMU 75
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2015-01-09 14:30:58 +00:00
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2018-06-11 16:15:35 +01:00
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/*******************************************************************************
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* Memprotect definitions
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******************************************************************************/
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/* PSCI memory protect definitions:
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* This variable is stored in a non-secure flash because some ARM reference
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* platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT
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* support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions.
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*/
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#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
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V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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2018-07-20 09:17:26 +01:00
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#endif /* JUNO_DEF_H */
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