59 lines
1.6 KiB
C
59 lines
1.6 KiB
C
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PLATFORM_DEF_H__
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#define __PLATFORM_DEF_H__
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#include <arch.h>
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#include <board_def.h>
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#include <common_def.h>
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stack */
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#if IMAGE_BL31
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#define PLATFORM_STACK_SIZE 0x800
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#else
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#define PLATFORM_STACK_SIZE 0x1000
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#endif
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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/*******************************************************************************
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* Memory layout constants
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******************************************************************************/
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/*
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* ARM-TF lives in SRAM, partition it here
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*/
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#define SHARED_RAM_BASE BL31_LIMIT
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#define SHARED_RAM_SIZE 0x00001000
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/*
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* BL3-1 specific defines.
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*
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* Put BL3-1 at the base of the Trusted SRAM, before SHARED_RAM.
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*/
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#define BL31_BASE SEC_SRAM_BASE
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#define BL31_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE)
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#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
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#define BL31_PROGBITS_LIMIT BL31_LIMIT
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#endif /* __PLATFORM_DEF_H__ */
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