2020-09-22 14:26:25 +01:00
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/*
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2021-08-26 06:19:02 +01:00
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* Copyright (c) 2020-2021, Arm Limited. All rights reserved.
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2020-09-22 14:26:25 +01:00
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MORELLO_DEF_H
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#define MORELLO_DEF_H
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/* Non-secure SRAM MMU mapping */
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#define MORELLO_NS_SRAM_BASE UL(0x06000000)
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#define MORELLO_NS_SRAM_SIZE UL(0x00010000)
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#define MORELLO_MAP_NS_SRAM MAP_REGION_FLAT( \
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MORELLO_NS_SRAM_BASE, \
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MORELLO_NS_SRAM_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/* SDS Platform information defines */
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#define MORELLO_SDS_PLATFORM_INFO_STRUCT_ID U(8)
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#define MORELLO_SDS_PLATFORM_INFO_OFFSET U(0)
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2021-01-20 12:27:31 +00:00
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#define MORELLO_SDS_PLATFORM_INFO_SIZE U(18)
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#define MORELLO_MAX_DDR_CAPACITY U(0x1000000000)
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2020-09-22 14:26:25 +01:00
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#define MORELLO_MAX_SLAVE_COUNT U(16)
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/* SDS BL33 image information defines */
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#define MORELLO_SDS_BL33_INFO_STRUCT_ID U(9)
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#define MORELLO_SDS_BL33_INFO_OFFSET U(0)
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#define MORELLO_SDS_BL33_INFO_SIZE U(12)
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/* Base address of non-secure SRAM where Platform information will be filled */
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2021-01-20 12:27:31 +00:00
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#define MORELLO_PLATFORM_INFO_BASE UL(0x06000000)
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2020-09-22 14:26:25 +01:00
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2021-08-26 06:19:02 +01:00
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/* DMC memory status registers */
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#define MORELLO_DMC0_MEMC_STATUS_REG 0x4E000000
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#define MORELLO_DMC1_MEMC_STATUS_REG 0x4E100000
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#define MORELLO_DMC_MEMC_STATUS_MASK U(7)
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/* DMC memory command registers */
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#define MORELLO_DMC0_MEMC_CMD_REG 0x4E000008
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#define MORELLO_DMC1_MEMC_CMD_REG 0x4E100008
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/* DMC ERR0CTLR0 registers */
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#define MORELLO_DMC0_ERR0CTLR0_REG 0x4E000708
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#define MORELLO_DMC1_ERR0CTLR0_REG 0x4E100708
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/* DMC ECC in ERR0CTLR0 register */
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#define MORELLO_DMC_ERR0CTLR0_ECC_EN U(9)
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/* DMC ERR2STATUS register */
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#define MORELLO_DMC0_ERR2STATUS_REG 0x4E000790
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#define MORELLO_DMC1_ERR2STATUS_REG 0x4E100790
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/* DMC memory commands */
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#define MORELLO_DMC_MEMC_CMD_CONFIG U(0)
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#define MORELLO_DMC_MEMC_CMD_READY U(3)
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2020-09-22 14:26:25 +01:00
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#endif /* MORELLO_DEF_H */
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