2019-03-06 09:15:06 +00:00
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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#define PLATFORM_STACK_SIZE 0xB00
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#define CACHE_WRITEBACK_GRANULE 64
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#define PLAT_PRIMARY_CPU 0x0
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#define PLATFORM_MAX_CPU_PER_CLUSTER 4
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#define PLATFORM_CLUSTER_COUNT 1
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#define PLATFORM_CLUSTER0_CORE_COUNT 4
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#define PLATFORM_CLUSTER1_CORE_COUNT 0
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
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#define IMX_PWR_LVL0 MPIDR_AFFLVL0
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#define IMX_PWR_LVL1 MPIDR_AFFLVL1
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#define IMX_PWR_LVL2 MPIDR_AFFLVL2
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#define PWR_DOMAIN_AT_MAX_LVL U(1)
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#define PLAT_MAX_PWR_LVL U(2)
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#define PLAT_MAX_OFF_STATE U(4)
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#define PLAT_MAX_RET_STATE U(2)
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#define PLAT_WAIT_RET_STATE U(1)
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#define PLAT_STOP_OFF_STATE U(3)
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#define BL31_BASE U(0x920000)
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#define BL31_LIMIT U(0x940000)
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#define BL32_BASE U(0xbe000000)
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/* non-secure uboot base */
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#define PLAT_NS_IMAGE_OFFSET U(0x40200000)
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/* GICv3 base address */
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#define PLAT_GICD_BASE U(0x38800000)
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#define PLAT_GICR_BASE U(0x38880000)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
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#define MAX_XLAT_TABLES 8
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#define MAX_MMAP_REGIONS 16
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#define HAB_RVT_BASE U(0x00000900) /* HAB_RVT for i.MX8MM */
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#define IMX_BOOT_UART_BASE U(0x30890000)
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#define IMX_BOOT_UART_CLK_IN_HZ 24000000 /* Select 24MHz oscillator */
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#define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE
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#define PLAT_CRASH_UART_CLK_IN_HZ 24000000
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#define IMX_CONSOLE_BAUDRATE 115200
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#define IMX_AIPSTZ1 U(0x301f0000)
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#define IMX_AIPSTZ2 U(0x305f0000)
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#define IMX_AIPSTZ3 U(0x309f0000)
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#define IMX_AIPSTZ4 U(0x32df0000)
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#define IMX_AIPS_BASE U(0x30000000)
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#define IMX_AIPS_SIZE U(0xC00000)
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#define IMX_GPV_BASE U(0x32000000)
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#define IMX_GPV_SIZE U(0x800000)
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#define IMX_AIPS1_BASE U(0x30200000)
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#define IMX_AIPS4_BASE U(0x32c00000)
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#define IMX_ANAMIX_BASE U(0x30360000)
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#define IMX_CCM_BASE U(0x30380000)
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#define IMX_SRC_BASE U(0x30390000)
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#define IMX_GPC_BASE U(0x303a0000)
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#define IMX_RDC_BASE U(0x303d0000)
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#define IMX_CSU_BASE U(0x303e0000)
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#define IMX_WDOG_BASE U(0x30280000)
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#define IMX_SNVS_BASE U(0x30370000)
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#define IMX_NOC_BASE U(0x32700000)
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#define IMX_TZASC_BASE U(0x32F80000)
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#define IMX_IOMUX_GPR_BASE U(0x30340000)
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2019-06-12 10:41:47 +01:00
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#define IMX_CAAM_BASE U(0x30900000)
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2019-03-06 09:15:06 +00:00
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#define IMX_DDRC_BASE U(0x3d400000)
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#define IMX_DDRPHY_BASE U(0x3c000000)
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#define IMX_DDR_IPS_BASE U(0x3d000000)
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#define IMX_ROM_BASE U(0x0)
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#define GPV_BASE U(0x32000000)
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#define GPV_SIZE U(0x800000)
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#define IMX_GIC_BASE PLAT_GICD_BASE
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#define IMX_GIC_SIZE U(0x200000)
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#define WDOG_WSR U(0x2)
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#define WDOG_WCR_WDZST BIT(0)
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#define WDOG_WCR_WDBG BIT(1)
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#define WDOG_WCR_WDE BIT(2)
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#define WDOG_WCR_WDT BIT(3)
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#define WDOG_WCR_SRS BIT(4)
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#define WDOG_WCR_WDA BIT(5)
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#define WDOG_WCR_SRE BIT(6)
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#define WDOG_WCR_WDW BIT(7)
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#define SRC_A53RCR0 U(0x4)
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#define SRC_A53RCR1 U(0x8)
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#define SRC_OTG1PHY_SCR U(0x20)
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#define SRC_OTG2PHY_SCR U(0x24)
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#define SRC_GPR1_OFFSET U(0x74)
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#define SNVS_LPCR U(0x38)
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#define SNVS_LPCR_SRTC_ENV BIT(0)
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#define SNVS_LPCR_DP_EN BIT(5)
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#define SNVS_LPCR_TOP BIT(6)
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#define IOMUXC_GPR10 U(0x28)
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#define GPR_TZASC_EN BIT(0)
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#define GPR_TZASC_EN_LOCK BIT(16)
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#define ANAMIX_MISC_CTL U(0x124)
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#define MAX_CSU_NUM U(64)
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#define OCRAM_S_BASE U(0x00180000)
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#define OCRAM_S_SIZE U(0x8000)
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#define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE)
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#define COUNTER_FREQUENCY 8000000 /* 8MHz */
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#define IMX_WDOG_B_RESET
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