2014-07-17 16:06:39 +01:00
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/*
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2016-01-21 14:08:15 +00:00
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* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
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2014-07-17 16:06:39 +01:00
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PLATFORM_DEF_H__
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#define __PLATFORM_DEF_H__
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2015-03-19 19:22:44 +00:00
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#include <arm_def.h>
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#include <board_arm_def.h>
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#include <board_css_def.h>
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#include <common_def.h>
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#include <css_def.h>
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#include <soc_css_def.h>
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#include <tzc400.h>
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#include <v2m_def.h>
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2014-07-17 09:56:29 +01:00
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#include "../juno_def.h"
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2014-07-17 16:06:39 +01:00
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2016-02-01 14:04:34 +00:00
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/* Required platform porting definitions */
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2015-05-08 10:18:59 +01:00
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/* Juno supports system power domain */
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#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2
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#define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \
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2016-02-01 14:04:34 +00:00
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JUNO_CLUSTER_COUNT + \
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2015-05-08 10:18:59 +01:00
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PLATFORM_CORE_COUNT)
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2016-02-01 14:04:34 +00:00
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#define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \
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JUNO_CLUSTER1_CORE_COUNT)
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2015-03-19 19:22:44 +00:00
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/*
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2015-05-08 10:18:59 +01:00
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* Other platform porting definitions are provided by included headers
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2015-03-19 19:22:44 +00:00
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*/
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2014-07-17 16:06:39 +01:00
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2015-03-19 19:22:44 +00:00
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/*
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* Required ARM standard platform porting definitions
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*/
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2016-02-01 14:04:34 +00:00
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#define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT
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2015-01-07 13:49:59 +00:00
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2015-03-19 19:22:44 +00:00
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/* Use the bypass address */
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#define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET
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2014-11-07 09:44:58 +00:00
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/*
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2015-03-19 19:22:44 +00:00
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* Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB
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* in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of
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* flash
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2014-11-07 09:44:58 +00:00
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*/
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2015-01-13 12:21:04 +00:00
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#if TRUSTED_BOARD_BOOT
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2015-03-19 19:22:44 +00:00
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#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000
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2015-01-13 12:21:04 +00:00
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#else
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2015-03-19 19:22:44 +00:00
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#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00010000
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#endif /* TRUSTED_BOARD_BOOT */
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2016-01-20 15:57:35 +00:00
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/*
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* If ARM_BOARD_OPTIMISE_MMAP=0 then Juno uses the default, unoptimised values
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* defined for ARM development platforms.
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*/
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#if ARM_BOARD_OPTIMISE_MMAP
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/*
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* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
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* plat_arm_mmap array defined for each BL stage.
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*/
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#if IMAGE_BL1
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# define PLAT_ARM_MMAP_ENTRIES 7
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# define MAX_XLAT_TABLES 4
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#endif
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#if IMAGE_BL2
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# define PLAT_ARM_MMAP_ENTRIES 8
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# define MAX_XLAT_TABLES 3
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#endif
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#if IMAGE_BL2U
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# define PLAT_ARM_MMAP_ENTRIES 4
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# define MAX_XLAT_TABLES 3
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#endif
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#if IMAGE_BL31
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# define PLAT_ARM_MMAP_ENTRIES 5
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# define MAX_XLAT_TABLES 2
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#endif
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#if IMAGE_BL32
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# define PLAT_ARM_MMAP_ENTRIES 4
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# define MAX_XLAT_TABLES 3
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#endif
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#endif /* ARM_BOARD_OPTIMISE_MMAP */
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2015-03-19 19:22:44 +00:00
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/* CCI related constants */
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#define PLAT_ARM_CCI_BASE 0x2c090000
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#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4
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#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3
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2016-01-21 14:08:15 +00:00
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/* System timer related constants */
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#define PLAT_ARM_NSTIMER_FRAME_ID 1
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2015-03-19 19:22:44 +00:00
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/* TZC related constants */
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2016-01-21 14:08:15 +00:00
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#define PLAT_ARM_TZC_BASE 0x2a4a0000
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2015-03-19 19:22:44 +00:00
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#define PLAT_ARM_TZC_NS_DEV_ACCESS ( \
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \
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TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT))
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2014-07-17 16:06:39 +01:00
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2014-11-07 09:44:58 +00:00
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/*
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2015-03-19 19:22:44 +00:00
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* Required ARM CSS based platform porting definitions
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2014-11-07 09:44:58 +00:00
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*/
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2015-03-19 19:22:44 +00:00
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/* GIC related constants (no GICR in GIC-400) */
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2015-11-03 14:18:34 +00:00
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#define PLAT_ARM_GICD_BASE 0x2c010000
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#define PLAT_ARM_GICC_BASE 0x2c02f000
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#define PLAT_ARM_GICH_BASE 0x2c04f000
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#define PLAT_ARM_GICV_BASE 0x2c06f000
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2016-01-21 14:08:15 +00:00
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/* MHU related constants */
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#define PLAT_CSS_MHU_BASE 0x2b1f0000
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2016-02-08 16:29:30 +00:00
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/*
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* Base address of the first memory region used for communication between AP
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* and SCP. Used by the BOM and SCPI protocols.
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*
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* Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which
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* means the SCP/AP configuration data gets overwritten when the AP initiates
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* communication with the SCP. The configuration data is expected to be a
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* 32-bit word on all CSS platforms. On Juno, part of this configuration is
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* which CPU is the primary, according to the shift and mask definitions below.
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*/
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#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80)
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#define PLAT_CSS_PRIMARY_CPU_SHIFT 8
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#define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4
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2015-11-03 14:18:34 +00:00
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define PLAT_ARM_G1S_IRQS CSS_G1S_IRQS, \
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ARM_G1S_IRQS, \
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2015-06-24 17:51:09 +01:00
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JUNO_IRQ_DMA_SMMU, \
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JUNO_IRQ_HDLCD0_SMMU, \
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JUNO_IRQ_HDLCD1_SMMU, \
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JUNO_IRQ_USB_SMMU, \
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JUNO_IRQ_THIN_LINKS_SMMU, \
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JUNO_IRQ_SEC_I2C, \
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JUNO_IRQ_GPU_SMMU_1, \
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JUNO_IRQ_ETR_SMMU
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2015-03-19 19:22:44 +00:00
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2015-11-03 14:18:34 +00:00
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#define PLAT_ARM_G0_IRQS ARM_G0_IRQS
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2014-11-07 09:44:58 +00:00
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/*
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2015-03-19 19:22:44 +00:00
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* Required ARM CSS SoC based platform porting definitions
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2014-11-07 09:44:58 +00:00
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*/
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2015-03-19 19:22:44 +00:00
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/* CSS SoC NIC-400 Global Programmers View (GPV) */
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#define PLAT_SOC_CSS_NIC400_BASE 0x2a000000
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2016-01-21 14:08:15 +00:00
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/*
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* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
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* plus a little space for growth.
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*/
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#if TRUSTED_BOARD_BOOT
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# define PLAT_ARM_MAX_BL1_RW_SIZE 0x9000
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#else
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# define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000
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#endif
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/*
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* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
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* little space for growth.
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*/
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#if TRUSTED_BOARD_BOOT
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# define PLAT_ARM_MAX_BL2_SIZE 0x1D000
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#else
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# define PLAT_ARM_MAX_BL2_SIZE 0xC000
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#endif
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/*
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* PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a
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* little space for growth.
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*/
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#define PLAT_ARM_MAX_BL31_SIZE 0x1D000
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2015-01-08 18:02:19 +00:00
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2014-07-17 16:06:39 +01:00
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#endif /* __PLATFORM_DEF_H__ */
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