2017-08-03 16:04:46 +01:00
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/*
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2019-02-11 13:34:15 +00:00
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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2017-08-03 16:04:46 +01:00
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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2018-11-08 10:20:19 +00:00
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#ifndef CORTEX_A76_H
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#define CORTEX_A76_H
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2017-08-03 16:04:46 +01:00
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2019-02-11 13:34:15 +00:00
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#include <lib/utils_def.h>
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2017-08-03 16:04:46 +01:00
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/* Cortex-A76 MIDR for revision 0 */
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2019-02-11 13:34:15 +00:00
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#define CORTEX_A76_MIDR U(0x410fd0b0)
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2017-08-03 16:04:46 +01:00
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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2019-02-11 13:34:15 +00:00
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#define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4
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2017-08-03 16:04:46 +01:00
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2018-05-16 09:59:54 +01:00
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1
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2019-02-11 13:34:15 +00:00
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#define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16)
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2018-05-16 09:59:54 +01:00
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2017-08-03 16:04:46 +01:00
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/* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */
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2019-02-11 13:34:15 +00:00
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#define CORTEX_A76_CORE_PWRDN_EN_MASK U(0x1)
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2017-08-03 16:04:46 +01:00
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2018-11-08 10:20:19 +00:00
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#endif /* CORTEX_A76_H */
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