Louis Mayencourt 5f5d1ed7d5 Add workaround for errata 764081 of Cortex-A75 ... Implicit Error Synchronization Barrier (IESB) might not be correctly generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all expection levels. Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>		2019-02-26 15:53:57 +00:00
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arch	Add workaround for errata 764081 of Cortex-A75	2019-02-26 15:53:57 +00:00
bl1	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
bl2	Standardise header guards across codebase	2018-11-08 10:20:19 +00:00
bl2u	Standardise header guards across codebase	2018-11-08 10:20:19 +00:00
bl31	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
bl32	tlkd: support new TLK SMCs	2019-01-31 08:46:54 -08:00
common	Merge pull request #1804 from antonio-nino-diaz-arm/an/cleanup	2019-02-05 11:31:15 +00:00
drivers	stm32mp1: add minimal support for co-processor Cortex-M4	2019-02-20 17:34:21 +01:00
dt-bindings	stm32mp1: update device tree files	2019-01-18 15:45:08 +01:00
lib	Add workaround for errata 855423 of Cortex-A73	2019-02-26 13:22:56 +00:00
plat	Rename PLAT_ARM_BL31_RUN_UART* variable	2019-02-18 14:44:28 +00:00
services	Remove support for the SMC Calling Convention 2.0	2019-01-30 16:01:49 +00:00
tools_share	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00