Louis Mayencourt 5f5d1ed7d5 Add workaround for errata 764081 of Cortex-A75 ... Implicit Error Synchronization Barrier (IESB) might not be correctly generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all expection levels. Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>		2019-02-26 15:53:57 +00:00
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aarch32	plat/arm: Support for Cortex A5 in FVP Versatile Express platform	2019-02-19 17:07:48 +00:00
aarch64	Add workaround for errata 764081 of Cortex-A75	2019-02-26 15:53:57 +00:00