Louis Mayencourt 5f5d1ed7d5 Add workaround for errata 764081 of Cortex-A75 ... Implicit Error Synchronization Barrier (IESB) might not be correctly generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all expection levels. Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>		2019-02-26 15:53:57 +00:00
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arch.h	Add workaround for errata 764081 of Cortex-A75	2019-02-26 15:53:57 +00:00
arch_features.h	drivers: generic_delay_timer: Assert presence of Generic Timer	2019-02-06 09:54:42 +00:00
arch_helpers.h	Helper function to read ID_AFR0_EL1 system register	2019-01-23 10:31:04 -08:00
asm_macros.S	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
assert_macros.S	Reorganize architecture-dependent header files	2019-01-04 10:43:16 +00:00
console_macros.S	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
el3_common_macros.S	Reorganize architecture-dependent header files	2019-01-04 10:43:16 +00:00
smccc_helpers.h	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00