228 lines
6.4 KiB
C
228 lines
6.4 KiB
C
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/*
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* Copyright (C) 2021 Sartura Ltd.
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* Copyright (C) 2021 Globalscale technologies, Inc.
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* Copyright (C) 2021 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <mv_ddr_if.h>
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#include <plat_marvell.h>
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/*
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* This function may modify the default DRAM parameters
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* based on information received from SPD or bootloader
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* configuration located on non volatile storage
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*/
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void plat_marvell_dram_update_topology(void)
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{
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}
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/*
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* This struct provides the DRAM training code with
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* the appropriate board DRAM configuration
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*/
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#if DDR_TOPOLOGY == 0
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static struct mv_ddr_topology_map board_topology_map_2g = {
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/* 1CS 4Gb x4 devices of Samsung K4A4G085WF */
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DEBUG_LEVEL_ERROR,
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
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{ { { {0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0} },
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SPEED_BIN_DDR_2400R, /* speed_bin */
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MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */
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MV_DDR_DIE_CAP_4GBIT, /* die capacity */
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MV_DDR_FREQ_SAR, /* frequency */
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0, 0, /* cas_l, cas_wl */
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MV_DDR_TEMP_LOW} }, /* temperature */
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BUS_MASK_32BIT, /* subphys mask */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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NOT_COMBINED, /* ddr twin-die combined*/
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{ {0} }, /* raw spd data */
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{0}, /* timing parameters */
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{ /* electrical configuration */
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{ /* memory electrical configuration */
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MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
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{
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MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */
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MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */
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},
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{
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MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */
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MV_DDR_RTT_WR_RZQ_DIV2 /* rtt_wr 2cs */
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},
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MV_DDR_DIC_RZQ_DIV7 /* dic */
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},
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{ /* phy electrical configuration */
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MV_DDR_OHM_30, /* data_drv_p */
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MV_DDR_OHM_30, /* data_drv_n */
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MV_DDR_OHM_30, /* ctrl_drv_p */
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MV_DDR_OHM_30, /* ctrl_drv_n */
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{
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MV_DDR_OHM_60, /* odt_p 1cs */
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MV_DDR_OHM_120 /* odt_p 2cs */
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},
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{
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MV_DDR_OHM_60, /* odt_n 1cs */
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MV_DDR_OHM_120 /* odt_n 2cs */
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},
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},
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{ /* mac electrical configuration */
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MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
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MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
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MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
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},
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}
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};
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#endif
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#if DDR_TOPOLOGY == 1
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static struct mv_ddr_topology_map board_topology_map_4g = {
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/* 1CS 8Gb x4 devices of Samsung K4A8G085WC-BCTD */
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DEBUG_LEVEL_ERROR,
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
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{ { { {0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0} },
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SPEED_BIN_DDR_2400R, /* speed_bin */
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MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */
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MV_DDR_DIE_CAP_8GBIT, /* die capacity */
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MV_DDR_FREQ_SAR, /* frequency */
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0, 0, /* cas_l, cas_wl */
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MV_DDR_TEMP_LOW} }, /* temperature */
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BUS_MASK_32BIT, /* subphys mask */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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NOT_COMBINED, /* ddr twin-die combined*/
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{ {0} }, /* raw spd data */
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{0}, /* timing parameters */
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{ /* electrical configuration */
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{ /* memory electrical configuration */
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MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
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{
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MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */
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MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */
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},
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{
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MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */
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MV_DDR_RTT_WR_RZQ_DIV2 /* rtt_wr 2cs */
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},
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MV_DDR_DIC_RZQ_DIV7 /* dic */
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},
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{ /* phy electrical configuration */
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MV_DDR_OHM_30, /* data_drv_p */
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MV_DDR_OHM_30, /* data_drv_n */
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MV_DDR_OHM_30, /* ctrl_drv_p */
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MV_DDR_OHM_30, /* ctrl_drv_n */
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{
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MV_DDR_OHM_60, /* odt_p 1cs */
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MV_DDR_OHM_120 /* odt_p 2cs */
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},
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{
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MV_DDR_OHM_60, /* odt_n 1cs */
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MV_DDR_OHM_120 /* odt_n 2cs */
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},
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},
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{ /* mac electrical configuration */
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MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
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MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
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MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
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},
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}
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};
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#endif
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#if DDR_TOPOLOGY == 2
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static struct mv_ddr_topology_map board_topology_map_8g = {
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/* 2CS 8Gb x8 devices of Micron MT40A1G8WE-083E IT */
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DEBUG_LEVEL_ERROR,
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
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{ { { {0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0} },
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SPEED_BIN_DDR_2400R, /* speed_bin */
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MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */
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MV_DDR_DIE_CAP_8GBIT, /* die capacity */
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MV_DDR_FREQ_SAR, /* frequency */
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0, 0, /* cas_l, cas_wl */
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MV_DDR_TEMP_LOW} }, /* temperature */
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BUS_MASK_32BIT, /* subphys mask */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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NOT_COMBINED, /* ddr twin-die combined*/
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{ {0} }, /* raw spd data */
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{0}, /* timing parameters */
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{ /* electrical configuration */
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{ /* memory electrical configuration */
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MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
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{
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MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */
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MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */
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},
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{
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MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */
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MV_DDR_RTT_WR_RZQ_DIV2 /* rtt_wr 2cs */
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},
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MV_DDR_DIC_RZQ_DIV7 /* dic */
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},
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{ /* phy electrical configuration */
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MV_DDR_OHM_30, /* data_drv_p */
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MV_DDR_OHM_30, /* data_drv_n */
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MV_DDR_OHM_30, /* ctrl_drv_p */
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MV_DDR_OHM_30, /* ctrl_drv_n */
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{
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MV_DDR_OHM_60, /* odt_p 1cs */
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MV_DDR_OHM_120 /* odt_p 2cs */
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},
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{
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MV_DDR_OHM_60, /* odt_n 1cs */
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MV_DDR_OHM_120 /* odt_n 2cs */
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},
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},
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{ /* mac electrical configuration */
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MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
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MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
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MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
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},
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}
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};
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#endif
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struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
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{
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/* a70x0_mochabin board supports 3 DDR4 models (2G/1CS, 4G/1CS, 8G/2CS) */
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#if DDR_TOPOLOGY == 0
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return &board_topology_map_2g;
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#elif DDR_TOPOLOGY == 1
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return &board_topology_map_4g;
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#elif DDR_TOPOLOGY == 2
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return &board_topology_map_8g;
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#else
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#error "Unknown DDR topology"
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#endif
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}
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