2018-04-10 01:48:58 +01:00
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/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl31/bl31.h>
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#include <common/bl_common.h>
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#include <common/interrupt_props.h>
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#include <drivers/console.h>
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#include <context.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <cortex_a57.h>
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#include <common/debug.h>
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#include <denver.h>
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#include <drivers/arm/gic_common.h>
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#include <drivers/arm/gicv2.h>
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#include <bl31/interrupt_mgmt.h>
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#include <mce.h>
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#include <plat/common/platform.h>
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#include <tegra_def.h>
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#include <tegra_platform.h>
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#include <tegra_private.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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/*******************************************************************************
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* The Tegra power domain tree has a single system level power domain i.e. a
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* single root node. The first entry in the power domain descriptor specifies
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* the number of power domains at the highest power level.
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*******************************************************************************
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*/
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const unsigned char tegra_power_domain_tree_desc[] = {
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/* No of root nodes */
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1,
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/* No of clusters */
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PLATFORM_CLUSTER_COUNT,
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/* No of CPU cores - cluster0 */
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PLATFORM_MAX_CPUS_PER_CLUSTER,
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/* No of CPU cores - cluster1 */
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PLATFORM_MAX_CPUS_PER_CLUSTER
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};
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2017-04-28 16:45:53 +01:00
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/*******************************************************************************
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* This function returns the Tegra default topology tree information.
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******************************************************************************/
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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return tegra_power_domain_tree_desc;
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}
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2018-04-10 01:48:58 +01:00
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/*
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* Table of regions to map using the MMU.
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*/
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static const mmap_region_t tegra_mmap[] = {
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MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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2017-01-24 08:46:07 +00:00
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MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000, /* 64KB */
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2018-04-10 01:48:58 +01:00
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MT_DEVICE | MT_RW | MT_SECURE),
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{0}
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};
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/*******************************************************************************
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* Set up the pagetables as per the platform memory map & initialize the MMU
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******************************************************************************/
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const mmap_region_t *plat_get_mmio_map(void)
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{
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/* MMIO space */
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return tegra_mmap;
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}
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/*******************************************************************************
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* Handler to get the System Counter Frequency
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******************************************************************************/
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unsigned int plat_get_syscnt_freq2(void)
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{
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return 31250000;
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}
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/*******************************************************************************
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* Maximum supported UART controllers
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******************************************************************************/
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#define TEGRA186_MAX_UART_PORTS 7
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/*******************************************************************************
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* This variable holds the UART port base addresses
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******************************************************************************/
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static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
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0, /* undefined - treated as an error case */
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TEGRA_UARTA_BASE,
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TEGRA_UARTB_BASE,
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TEGRA_UARTC_BASE,
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TEGRA_UARTD_BASE,
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TEGRA_UARTE_BASE,
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TEGRA_UARTF_BASE,
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TEGRA_UARTG_BASE,
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};
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/*******************************************************************************
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* Retrieve the UART controller base to be used as the console
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******************************************************************************/
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uint32_t plat_get_console_from_id(int id)
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{
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if (id > TEGRA186_MAX_UART_PORTS)
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return 0;
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return tegra186_uart_addresses[id];
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}
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/*******************************************************************************
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* Handler for early platform setup
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******************************************************************************/
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void plat_early_platform_setup(void)
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{
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/* sanity check MCE firmware compatibility */
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mce_verify_firmware_version();
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}
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/* Secure IRQs for Tegra186 */
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static const irq_sec_cfg_t tegra186_sec_irqs[] = {
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[0] = {
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TEGRA186_BPMP_WDT_IRQ,
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TEGRA186_SEC_IRQ_TARGET_MASK,
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INTR_TYPE_EL3,
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},
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[1] = {
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TEGRA186_BPMP_WDT_IRQ,
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TEGRA186_SEC_IRQ_TARGET_MASK,
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INTR_TYPE_EL3,
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},
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[2] = {
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TEGRA186_SPE_WDT_IRQ,
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TEGRA186_SEC_IRQ_TARGET_MASK,
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INTR_TYPE_EL3,
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},
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[3] = {
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TEGRA186_SCE_WDT_IRQ,
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TEGRA186_SEC_IRQ_TARGET_MASK,
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INTR_TYPE_EL3,
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},
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[4] = {
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TEGRA186_TOP_WDT_IRQ,
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TEGRA186_SEC_IRQ_TARGET_MASK,
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INTR_TYPE_EL3,
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},
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[5] = {
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TEGRA186_AON_WDT_IRQ,
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TEGRA186_SEC_IRQ_TARGET_MASK,
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INTR_TYPE_EL3,
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},
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};
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/*******************************************************************************
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* Initialize the GIC and SGIs
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******************************************************************************/
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void plat_gic_setup(void)
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{
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tegra_gic_setup(tegra186_sec_irqs,
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sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0]));
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/*
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* Initialize the FIQ handler only if the platform supports any
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* FIQ interrupt sources.
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*/
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if (sizeof(tegra186_sec_irqs) > 0)
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tegra_fiq_handler_setup();
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}
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/*******************************************************************************
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* Return pointer to the BL31 params from previous bootloader
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******************************************************************************/
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struct tegra_bl31_params *plat_get_bl31_params(void)
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{
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uint32_t val;
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val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO);
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return (struct tegra_bl31_params *)(uintptr_t)val;
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}
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/*******************************************************************************
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* Return pointer to the BL31 platform params from previous bootloader
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******************************************************************************/
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plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
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{
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uint32_t val;
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val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI);
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return (plat_params_from_bl2_t *)(uintptr_t)val;
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}
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