2017-01-02 14:13:45 +00:00
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/*
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2018-04-19 08:41:43 +01:00
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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2017-01-02 14:13:45 +00:00
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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2017-05-31 19:41:00 +01:00
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#include <common/bl_common.h>
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#include <common/debug.h>
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2017-01-02 14:13:45 +00:00
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#include <smmu.h>
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2017-05-31 19:41:00 +01:00
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#include <tegra_def.h>
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2017-01-02 14:13:45 +00:00
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2017-07-25 05:44:32 +01:00
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#define BOARD_SYSTEM_FPGA_BASE U(1)
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#define BASE_CONFIG_SMMU_DEVICES U(2)
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#define MAX_NUM_SMMU_DEVICES U(3)
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static uint32_t tegra_misc_read_32(uint32_t off)
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{
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2017-09-20 10:44:43 +01:00
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return mmio_read_32((uintptr_t)TEGRA_MISC_BASE + off);
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2017-07-25 05:44:32 +01:00
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}
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/*******************************************************************************
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* Handler to return the support SMMU devices number
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******************************************************************************/
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uint32_t plat_get_num_smmu_devices(void)
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{
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uint32_t ret_num = MAX_NUM_SMMU_DEVICES;
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uint32_t board_revid = ((tegra_misc_read_32(MISCREG_EMU_REVID) >> \
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2017-08-03 14:42:14 +01:00
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BOARD_SHIFT_BITS) & BOARD_MASK_BITS);
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2017-07-25 05:44:32 +01:00
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if (board_revid == BOARD_SYSTEM_FPGA_BASE) {
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ret_num = BASE_CONFIG_SMMU_DEVICES;
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}
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return ret_num;
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2017-11-10 19:04:42 +00:00
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}
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