2016-11-09 16:29:02 +00:00
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/*
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2018-01-16 10:32:47 +00:00
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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2016-11-09 16:29:02 +00:00
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl_common.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include <cortex_a75.h>
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2017-12-11 11:45:35 +00:00
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.globl cortex_a75_amu_cnt_read
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.globl cortex_a75_amu_cnt_write
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.globl cortex_a75_amu_read_cpuamcntenset_el0
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.globl cortex_a75_amu_read_cpuamcntenclr_el0
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.globl cortex_a75_amu_write_cpuamcntenset_el0
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.globl cortex_a75_amu_write_cpuamcntenclr_el0
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/*
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* uint64_t cortex_a75_amu_cnt_read(int idx);
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*
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* Given `idx`, read the corresponding AMU counter
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* and return it in `x0`.
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*/
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func cortex_a75_amu_cnt_read
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adr x1, 1f
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lsl x0, x0, #3
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add x1, x1, x0
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br x1
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1:
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mrs x0, CPUAMEVCNTR0_EL0
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ret
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mrs x0, CPUAMEVCNTR1_EL0
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ret
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mrs x0, CPUAMEVCNTR2_EL0
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ret
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mrs x0, CPUAMEVCNTR3_EL0
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ret
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mrs x0, CPUAMEVCNTR4_EL0
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ret
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endfunc cortex_a75_amu_cnt_read
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/*
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* void cortex_a75_amu_cnt_write(int idx, uint64_t val);
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*
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* Given `idx`, write `val` to the corresponding AMU counter.
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*/
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func cortex_a75_amu_cnt_write
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adr x2, 1f
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lsl x0, x0, #3
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add x2, x2, x0
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br x2
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1:
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msr CPUAMEVCNTR0_EL0, x0
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ret
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msr CPUAMEVCNTR1_EL0, x0
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ret
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msr CPUAMEVCNTR2_EL0, x0
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ret
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msr CPUAMEVCNTR3_EL0, x0
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ret
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msr CPUAMEVCNTR4_EL0, x0
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ret
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endfunc cortex_a75_amu_cnt_write
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/*
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* unsigned int cortex_a75_amu_read_cpuamcntenset_el0(void);
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*
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* Read the `CPUAMCNTENSET_EL0` CPU register and return
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* it in `x0`.
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*/
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func cortex_a75_amu_read_cpuamcntenset_el0
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mrs x0, CPUAMCNTENSET_EL0
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ret
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endfunc cortex_a75_amu_read_cpuamcntenset_el0
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/*
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* unsigned int cortex_a75_amu_read_cpuamcntenclr_el0(void);
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*
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* Read the `CPUAMCNTENCLR_EL0` CPU register and return
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* it in `x0`.
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*/
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func cortex_a75_amu_read_cpuamcntenclr_el0
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mrs x0, CPUAMCNTENCLR_EL0
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ret
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endfunc cortex_a75_amu_read_cpuamcntenclr_el0
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/*
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* void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask);
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*
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* Write `mask` to the `CPUAMCNTENSET_EL0` CPU register.
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*/
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func cortex_a75_amu_write_cpuamcntenset_el0
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msr CPUAMCNTENSET_EL0, x0
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ret
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endfunc cortex_a75_amu_write_cpuamcntenset_el0
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/*
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* void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask);
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*
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* Write `mask` to the `CPUAMCNTENCLR_EL0` CPU register.
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*/
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func cortex_a75_amu_write_cpuamcntenclr_el0
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mrs x0, CPUAMCNTENCLR_EL0
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ret
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endfunc cortex_a75_amu_write_cpuamcntenclr_el0
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2017-10-16 11:40:10 +01:00
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func cortex_a75_reset_func
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2017-12-18 13:46:21 +00:00
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#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
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2018-01-02 15:53:01 +00:00
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mrs x0, id_aa64pfr0_el1
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ubfx x0, x0, #ID_AA64PFR0_CSV2_SHIFT, #ID_AA64PFR0_CSV2_LENGTH
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/*
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* If the field equals to 1 then branch targets trained in one
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* context cannot affect speculative execution in a different context.
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*/
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cmp x0, #1
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beq 1f
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2017-12-18 13:46:21 +00:00
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adr x0, workaround_bpiall_vbar0_runtime_exceptions
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msr vbar_el3, x0
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2018-01-02 15:53:01 +00:00
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1:
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2017-12-18 13:46:21 +00:00
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#endif
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2017-10-16 11:40:10 +01:00
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT
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msr actlr_el3, x0
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isb
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/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
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mrs x0, actlr_el2
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orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT
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msr actlr_el2, x0
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isb
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/* Enable group0 counters */
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mov x0, #CORTEX_A75_AMU_GROUP0_MASK
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msr CPUAMCNTENSET_EL0, x0
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isb
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/* Enable group1 counters */
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mov x0, #CORTEX_A75_AMU_GROUP1_MASK
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msr CPUAMCNTENSET_EL0, x0
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isb
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#endif
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ret
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endfunc cortex_a75_reset_func
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2018-01-16 10:32:47 +00:00
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func check_errata_cve_2017_5715
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mrs x0, id_aa64pfr0_el1
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ubfx x0, x0, #ID_AA64PFR0_CSV2_SHIFT, #ID_AA64PFR0_CSV2_LENGTH
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/*
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* If the field equals to 1 then branch targets trained in one
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* context cannot affect speculative execution in a different context.
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*/
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cmp x0, #1
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beq 1f
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#if WORKAROUND_CVE_2017_5715
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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1:
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mov x0, #ERRATA_NOT_APPLIES
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ret
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endfunc check_errata_cve_2017_5715
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2016-11-09 16:29:02 +00:00
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func cortex_a75_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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mrs x0, CORTEX_A75_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK
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msr CORTEX_A75_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_a75_core_pwr_dwn
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2018-01-16 10:32:47 +00:00
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex A75. Must follow AAPCS.
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*/
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func cortex_a75_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a75_errata_report
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#endif
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2016-11-09 16:29:02 +00:00
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/* ---------------------------------------------
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* This function provides cortex_a75 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a75_regs, "aS"
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cortex_a75_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a75_cpu_reg_dump
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adr x6, cortex_a75_regs
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mrs x8, CORTEX_A75_CPUECTLR_EL1
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ret
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endfunc cortex_a75_cpu_reg_dump
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declare_cpu_ops cortex_a75, CORTEX_A75_MIDR, \
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2017-10-16 11:40:10 +01:00
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cortex_a75_reset_func, \
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2016-11-09 16:29:02 +00:00
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cortex_a75_core_pwr_dwn
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