63 lines
2.6 KiB
C
63 lines
2.6 KiB
C
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __UART8250_H__
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#define __UART8250_H__
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/* UART register */
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#define UART_RBR 0x00 /* Receive buffer register */
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#define UART_DLL 0x00 /* Divisor latch lsb */
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#define UART_THR 0x00 /* Transmit holding register */
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#define UART_DLH 0x04 /* Divisor latch msb */
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#define UART_IER 0x04 /* Interrupt enable register */
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#define UART_FCR 0x08 /* FIFO control register */
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#define UART_LCR 0x0c /* Line control register */
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#define UART_MCR 0x10 /* Modem control register */
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#define UART_LSR 0x14 /* Line status register */
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#define UART_HIGHSPEED 0x24 /* High speed UART */
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/* FCR */
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#define UART_FCR_FIFO_EN 0x01 /* enable FIFO */
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#define UART_FCR_CLEAR_RCVR 0x02 /* clear the RCVR FIFO */
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#define UART_FCR_CLEAR_XMIT 0x04 /* clear the XMIT FIFO */
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/* LCR */
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#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
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#define UART_LCR_DLAB 0x80 /* divisor latch access bit */
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/* MCR */
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#define UART_MCR_DTR 0x01
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#define UART_MCR_RTS 0x02
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/* LSR */
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#define UART_LSR_DR 0x01 /* Data ready */
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#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
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#endif /* __UART8250_H__ */
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