2015-05-19 12:18:04 +01:00
|
|
|
/*
|
2017-03-13 07:34:08 +00:00
|
|
|
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
|
2015-05-19 12:18:04 +01:00
|
|
|
*
|
2017-05-03 09:38:09 +01:00
|
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
2015-05-19 12:18:04 +01:00
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef __TEGRA_PRIVATE_H__
|
|
|
|
#define __TEGRA_PRIVATE_H__
|
|
|
|
|
2015-08-07 05:33:00 +01:00
|
|
|
#include <arch.h>
|
2015-05-19 12:18:04 +01:00
|
|
|
#include <platform_def.h>
|
2015-12-09 14:22:47 +00:00
|
|
|
#include <psci.h>
|
2018-02-17 05:02:32 +00:00
|
|
|
#include <xlat_tables_v2.h>
|
2015-05-19 12:18:04 +01:00
|
|
|
|
2015-06-10 09:34:32 +01:00
|
|
|
/*******************************************************************************
|
|
|
|
* Tegra DRAM memory base address
|
|
|
|
******************************************************************************/
|
2017-04-24 22:17:12 +01:00
|
|
|
#define TEGRA_DRAM_BASE ULL(0x80000000)
|
|
|
|
#define TEGRA_DRAM_END ULL(0x27FFFFFFF)
|
2015-06-10 09:34:32 +01:00
|
|
|
|
2015-12-28 22:55:41 +00:00
|
|
|
/*******************************************************************************
|
|
|
|
* Struct for parameters received from BL2
|
|
|
|
******************************************************************************/
|
2015-05-19 12:18:04 +01:00
|
|
|
typedef struct plat_params_from_bl2 {
|
2015-10-06 08:19:31 +01:00
|
|
|
/* TZ memory size */
|
2015-05-19 12:18:04 +01:00
|
|
|
uint64_t tzdram_size;
|
2015-10-06 08:19:31 +01:00
|
|
|
/* TZ memory base */
|
|
|
|
uint64_t tzdram_base;
|
2015-10-29 05:07:28 +00:00
|
|
|
/* UART port ID */
|
|
|
|
int uart_id;
|
2015-05-19 12:18:04 +01:00
|
|
|
} plat_params_from_bl2_t;
|
|
|
|
|
2015-12-29 00:36:42 +00:00
|
|
|
/*******************************************************************************
|
|
|
|
* Per-CPU struct describing FIQ state to be stored
|
|
|
|
******************************************************************************/
|
|
|
|
typedef struct pcpu_fiq_state {
|
|
|
|
uint64_t elr_el3;
|
|
|
|
uint64_t spsr_el3;
|
|
|
|
} pcpu_fiq_state_t;
|
|
|
|
|
2016-05-21 00:21:22 +01:00
|
|
|
/*******************************************************************************
|
|
|
|
* Struct describing per-FIQ configuration settings
|
|
|
|
******************************************************************************/
|
|
|
|
typedef struct irq_sec_cfg {
|
|
|
|
/* IRQ number */
|
|
|
|
unsigned int irq;
|
|
|
|
/* Target CPUs servicing this interrupt */
|
|
|
|
unsigned int target_cpus;
|
|
|
|
/* type = INTR_TYPE_S_EL1 or INTR_TYPE_EL3 */
|
|
|
|
uint32_t type;
|
|
|
|
} irq_sec_cfg_t;
|
|
|
|
|
2015-07-23 05:37:54 +01:00
|
|
|
/* Declarations for plat_psci_handlers.c */
|
2015-08-07 05:33:00 +01:00
|
|
|
int32_t tegra_soc_validate_power_state(unsigned int power_state,
|
|
|
|
psci_power_state_t *req_state);
|
2015-07-23 05:37:54 +01:00
|
|
|
|
2015-05-19 12:18:04 +01:00
|
|
|
/* Declarations for plat_setup.c */
|
|
|
|
const mmap_region_t *plat_get_mmio_map(void);
|
2015-10-29 05:07:28 +00:00
|
|
|
uint32_t plat_get_console_from_id(int id);
|
2015-12-28 22:55:41 +00:00
|
|
|
void plat_gic_setup(void);
|
2016-05-23 19:41:07 +01:00
|
|
|
bl31_params_t *plat_get_bl31_params(void);
|
|
|
|
plat_params_from_bl2_t *plat_get_bl31_plat_params(void);
|
2015-05-19 12:18:04 +01:00
|
|
|
|
|
|
|
/* Declarations for plat_secondary.c */
|
|
|
|
void plat_secondary_setup(void);
|
|
|
|
int plat_lock_cpu_vectors(void);
|
|
|
|
|
2015-12-29 00:36:42 +00:00
|
|
|
/* Declarations for tegra_fiq_glue.c */
|
|
|
|
void tegra_fiq_handler_setup(void);
|
|
|
|
int tegra_fiq_get_intr_context(void);
|
|
|
|
void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint);
|
|
|
|
|
2015-05-19 12:18:04 +01:00
|
|
|
/* Declarations for tegra_gic.c */
|
|
|
|
void tegra_gic_cpuif_deactivate(void);
|
2017-05-26 02:06:59 +01:00
|
|
|
void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, uint32_t num_irqs);
|
2015-05-19 12:18:04 +01:00
|
|
|
|
|
|
|
/* Declarations for tegra_security.c */
|
|
|
|
void tegra_security_setup(void);
|
|
|
|
void tegra_security_setup_videomem(uintptr_t base, uint64_t size);
|
|
|
|
|
|
|
|
/* Declarations for tegra_pm.c */
|
2017-03-03 18:58:05 +00:00
|
|
|
extern uint8_t tegra_fake_system_suspend;
|
|
|
|
|
2015-05-19 12:18:04 +01:00
|
|
|
void tegra_pm_system_suspend_entry(void);
|
|
|
|
void tegra_pm_system_suspend_exit(void);
|
|
|
|
int tegra_system_suspended(void);
|
|
|
|
|
|
|
|
/* Declarations for tegraXXX_pm.c */
|
|
|
|
int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl);
|
|
|
|
int tegra_prepare_cpu_on_finish(unsigned long mpidr);
|
|
|
|
|
|
|
|
/* Declarations for tegra_bl31_setup.c */
|
|
|
|
plat_params_from_bl2_t *bl31_get_plat_params(void);
|
2015-06-10 09:34:32 +01:00
|
|
|
int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes);
|
2016-03-28 23:56:47 +01:00
|
|
|
void plat_early_platform_setup(void);
|
2015-05-19 12:18:04 +01:00
|
|
|
|
2015-07-16 11:17:03 +01:00
|
|
|
/* Declarations for tegra_delay_timer.c */
|
|
|
|
void tegra_delay_timer_init(void);
|
|
|
|
|
2016-03-18 20:07:33 +00:00
|
|
|
void tegra_secure_entrypoint(void);
|
|
|
|
void tegra186_cpu_reset_handler(void);
|
|
|
|
|
2015-05-19 12:18:04 +01:00
|
|
|
#endif /* __TEGRA_PRIVATE_H__ */
|