2018-09-23 08:36:13 +01:00
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/*
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* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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2018-11-08 10:20:19 +00:00
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#ifndef RCAR_DEF_H
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#define RCAR_DEF_H
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2018-09-23 08:36:13 +01:00
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2018-12-14 00:18:21 +00:00
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#include <common/tbbr/tbbr_img_def.h>
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#include <lib/utils_def.h>
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2018-09-23 08:36:13 +01:00
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#define RCAR_PRIMARY_CPU 0x0
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#define RCAR_TRUSTED_SRAM_BASE 0x44000000
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#define RCAR_TRUSTED_SRAM_SIZE 0x0003E000
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#define RCAR_SHARED_MEM_BASE (RCAR_TRUSTED_SRAM_BASE + \
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RCAR_TRUSTED_SRAM_SIZE)
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#define RCAR_SHARED_MEM_SIZE U(0x00001000)
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#define FLASH0_BASE U(0x08000000)
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#define FLASH0_SIZE U(0x04000000)
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#define FLASH_MEMORY_SIZE U(0x04000000) /* hyper flash */
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#define FLASH_TRANS_SIZE_UNIT U(0x00000100)
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#define DEVICE_RCAR_BASE U(0xE6000000)
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#define DEVICE_RCAR_SIZE U(0x00300000)
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#define DEVICE_RCAR_BASE2 U(0xE6360000)
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#define DEVICE_RCAR_SIZE2 U(0x19CA0000)
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2018-12-26 14:57:08 +00:00
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#define DEVICE_SRAM_BASE U(0xE6300000)
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2018-09-23 08:36:13 +01:00
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#define DEVICE_SRAM_SIZE U(0x00002000)
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#define DEVICE_SRAM_STACK_BASE (DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE)
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#define DEVICE_SRAM_STACK_SIZE U(0x00001000)
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#define DRAM_LIMIT ULL(0x0000010000000000)
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#define DRAM1_BASE U(0x40000000)
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#define DRAM1_SIZE U(0x80000000)
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#define DRAM1_NS_BASE (DRAM1_BASE + U(0x10000000))
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#define DRAM1_NS_SIZE (DRAM1_SIZE - DRAM1_NS_BASE)
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#define DRAM_40BIT_BASE ULL(0x0400000000)
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#define DRAM_40BIT_SIZE ULL(0x0400000000)
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#define DRAM_PROTECTED_BASE ULL(0x43F00000)
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#define DRAM_40BIT_PROTECTED_BASE ULL(0x0403F00000)
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#define DRAM_PROTECTED_SIZE ULL(0x03F00000)
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#define RCAR_BL31_CRASH_BASE U(0x4403F000)
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#define RCAR_BL31_CRASH_SIZE U(0x00001000)
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/* Entrypoint mailboxes */
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#define MBOX_BASE RCAR_SHARED_MEM_BASE
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#define MBOX_SIZE 0x200
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/* Base address where parameters to BL31 are stored */
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#define PARAMS_BASE (MBOX_BASE + MBOX_SIZE)
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#define BOOT_KIND_BASE (RCAR_SHARED_MEM_BASE + \
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RCAR_SHARED_MEM_SIZE - 0x100)
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/* The number of regions like RO(code), coherent and data required by
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* different BL stages which need to be mapped in the MMU */
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#if USE_COHERENT_MEM
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#define RCAR_BL_REGIONS (3)
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#else
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#define RCAR_BL_REGIONS (2)
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#endif
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/* The RCAR_MAX_MMAP_REGIONS depend on the number of entries in rcar_mmap[]
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* defined for each BL stage in rcar_common.c. */
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#if IMAGE_BL2
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#define RCAR_MMAP_ENTRIES (9)
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#endif
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#if IMAGE_BL31
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#define RCAR_MMAP_ENTRIES (9)
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#endif
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#if IMAGE_BL2
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#define REG1_BASE U(0xE6400000)
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#define REG1_SIZE U(0x04C00000)
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#define ROM0_BASE U(0xEB100000)
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#define ROM0_SIZE U(0x00028000)
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#define REG2_BASE U(0xEC000000)
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#define REG2_SIZE U(0x14000000)
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#endif
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/* BL33 */
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#define NS_IMAGE_OFFSET (DRAM1_BASE + U(0x09000000))
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/* BL31 */
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#define RCAR_DEVICE_BASE DEVICE_RCAR_BASE
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#define RCAR_DEVICE_SIZE (0x1A000000)
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#define RCAR_LOG_RES_SIZE (512/8)
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#define RCAR_LOG_HEADER_SIZE (16)
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#define RCAR_LOG_OTHER_SIZE (RCAR_LOG_HEADER_SIZE + \
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RCAR_LOG_RES_SIZE)
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#define RCAR_BL31_LOG_MAX (RCAR_BL31_LOG_SIZE - \
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RCAR_LOG_OTHER_SIZE)
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#define RCAR_CRASH_STACK RCAR_BL31_CRASH_BASE
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#define AARCH64_SPACE_BASE ULL(0x00000000000)
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#define AARCH64_SPACE_SIZE ULL(0x10000000000)
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/* CCI related constants */
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#define CCI500_BASE U(0xF1200000)
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#define CCI500_CLUSTER0_SL_IFACE_IX (2)
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#define CCI500_CLUSTER1_SL_IFACE_IX (3)
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#define CCI500_CLUSTER0_SL_IFACE_IX_FOR_M3 (1)
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#define CCI500_CLUSTER1_SL_IFACE_IX_FOR_M3 (2)
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#define RCAR_CCI_BASE CCI500_BASE
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/* GIC */
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#define RCAR_GICD_BASE U(0xF1010000)
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#define RCAR_GICR_BASE U(0xF1010000)
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#define RCAR_GICC_BASE U(0xF1020000)
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#define RCAR_GICH_BASE U(0xF1040000)
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#define RCAR_GICV_BASE U(0xF1060000)
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#define ARM_IRQ_SEC_PHY_TIMER U(29)
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#define ARM_IRQ_SEC_SGI_0 U(8)
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#define ARM_IRQ_SEC_SGI_1 U(9)
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#define ARM_IRQ_SEC_SGI_2 U(10)
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#define ARM_IRQ_SEC_SGI_3 U(11)
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#define ARM_IRQ_SEC_SGI_4 U(12)
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#define ARM_IRQ_SEC_SGI_5 U(13)
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#define ARM_IRQ_SEC_SGI_6 U(14)
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#define ARM_IRQ_SEC_SGI_7 U(15)
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#define ARM_IRQ_SEC_RPC U(70)
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#define ARM_IRQ_SEC_TIMER U(166)
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#define ARM_IRQ_SEC_TIMER_UP U(171)
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#define ARM_IRQ_SEC_WDT U(173)
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#define ARM_IRQ_SEC_CRYPT U(102)
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#define ARM_IRQ_SEC_CRYPT_SecPKA U(97)
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#define ARM_IRQ_SEC_CRYPT_PubPKA U(98)
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/* Timer control */
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#define RCAR_CNTC_BASE U(0xE6080000)
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/* Reset */
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#define RCAR_CPGWPR U(0xE6150900) /* CPG write protect */
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#define RCAR_MODEMR U(0xE6160060) /* Mode pin */
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#define RCAR_CA57RESCNT U(0xE6160040) /* Reset control A57 */
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#define RCAR_CA53RESCNT U(0xE6160044) /* Reset control A53 */
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#define RCAR_SRESCR U(0xE6160110) /* Soft Power On Reset */
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#define RCAR_CA53WUPCR U(0xE6151010) /* Wake-up control A53 */
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#define RCAR_CA57WUPCR U(0xE6152010) /* Wake-up control A57 */
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#define RCAR_CA53PSTR U(0xE6151040) /* Power status A53 */
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#define RCAR_CA57PSTR U(0xE6152040) /* Power status A57 */
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#define RCAR_CA53CPU0CR U(0xE6151100) /* CPU control A53 */
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#define RCAR_CA57CPU0CR U(0xE6152100) /* CPU control A57 */
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#define RCAR_CA53CPUCMCR U(0xE6151184) /* Common power A53 */
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#define RCAR_CA57CPUCMCR U(0xE6152184) /* Common power A57 */
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#define RCAR_WUPMSKCA57 U(0xE6180014) /* Wake-up mask A57 */
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#define RCAR_WUPMSKCA53 U(0xE6180018) /* Wake-up mask A53 */
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/* SYSC */
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#define RCAR_PWRSR3 U(0xE6180140) /* Power stat A53-SCU */
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#define RCAR_PWRSR5 U(0xE61801C0) /* Power stat A57-SCU */
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#define RCAR_SYSCIER U(0xE618000C) /* Interrupt enable */
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#define RCAR_SYSCIMR U(0xE6180010) /* Interrupt mask */
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#define RCAR_SYSCSR U(0xE6180000) /* SYSC status */
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#define RCAR_PWRONCR3 U(0xE618014C) /* Power resume A53-SCU */
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#define RCAR_PWRONCR5 U(0xE61801CC) /* Power resume A57-SCU */
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#define RCAR_PWROFFCR3 U(0xE6180144) /* Power shutof A53-SCU */
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#define RCAR_PWROFFCR5 U(0xE61801C4) /* Power shutof A57-SCU */
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#define RCAR_PWRER3 U(0xE6180154) /* shutoff/resume error */
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#define RCAR_PWRER5 U(0xE61801D4) /* shutoff/resume error */
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#define RCAR_SYSCISR U(0xE6180004) /* Interrupt status */
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#define RCAR_SYSCISCR U(0xE6180008) /* Interrupt stat clear */
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/* Product register */
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#define RCAR_PRR U(0xFFF00044)
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#define RCAR_PRODUCT_MASK U(0x00007F00)
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#define RCAR_CUT_MASK U(0x000000FF)
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#define RCAR_PRODUCT_H3 U(0x00004F00)
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#define RCAR_PRODUCT_M3 U(0x00005200)
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#define RCAR_PRODUCT_M3N U(0x00005500)
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#define RCAR_PRODUCT_E3 U(0x00005700)
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#define RCAR_CUT_VER10 U(0x00000000)
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2019-02-25 13:57:08 +00:00
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#define RCAR_CUT_VER11 U(0x00000001) /* H3/M3N/E3 Ver.1.1 */
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2018-09-23 08:36:13 +01:00
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#define RCAR_M3_CUT_VER11 U(0x00000010) /* M3 Ver.1.1/Ver.1.2 */
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#define RCAR_CUT_VER20 U(0x00000010)
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#define RCAR_CUT_VER30 U(0x00000020)
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#define RCAR_MAJOR_MASK U(0x000000F0)
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#define RCAR_MINOR_MASK U(0x0000000F)
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#define RCAR_PRODUCT_SHIFT U(8)
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#define RCAR_MAJOR_SHIFT U(4)
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#define RCAR_MINOR_SHIFT U(0)
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#define RCAR_MAJOR_OFFSET U(1)
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2019-02-25 13:57:08 +00:00
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#define RCAR_M3_MINOR_OFFSET U(2)
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2018-09-23 08:36:13 +01:00
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#define RCAR_PRODUCT_H3_CUT10 (RCAR_PRODUCT_H3 | U(0x00)) /* 1.0 */
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#define RCAR_PRODUCT_H3_CUT11 (RCAR_PRODUCT_H3 | U(0x01)) /* 1.1 */
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#define RCAR_PRODUCT_H3_CUT20 (RCAR_PRODUCT_H3 | U(0x10)) /* 2.0 */
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#define RCAR_PRODUCT_M3_CUT10 (RCAR_PRODUCT_M3 | U(0x00)) /* 1.0 */
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#define RCAR_PRODUCT_M3_CUT11 (RCAR_PRODUCT_M3 | U(0x10))
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#define RCAR_CPU_MASK_CA57 U(0x80000000)
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#define RCAR_CPU_MASK_CA53 U(0x04000000)
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#define RCAR_CPU_HAVE_CA57 U(0x00000000)
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#define RCAR_CPU_HAVE_CA53 U(0x00000000)
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#define RCAR_SSCG_MASK U(0x1000) /* MD12 */
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#define RCAR_SSCG_ENABLE U(0x1000)
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/* MD pin information */
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#define MODEMR_BOOT_CPU_MASK U(0x000000C0)
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#define MODEMR_BOOT_CPU_CR7 U(0x000000C0)
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#define MODEMR_BOOT_CPU_CA57 U(0x00000000)
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#define MODEMR_BOOT_CPU_CA53 U(0x00000040)
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#define MODEMR_BOOT_DEV_MASK U(0x0000001E)
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#define MODEMR_BOOT_DEV_HYPERFLASH160 U(0x00000004)
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#define MODEMR_BOOT_DEV_HYPERFLASH80 U(0x00000006)
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#define MODEMR_BOOT_DEV_QSPI_FLASH40 U(0x00000008)
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#define MODEMR_BOOT_DEV_QSPI_FLASH80 U(0x0000000C)
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#define MODEMR_BOOT_DEV_EMMC_25X1 U(0x0000000A)
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#define MODEMR_BOOT_DEV_EMMC_50X8 U(0x0000001A)
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#define MODEMR_BOOT_PLL_MASK U(0x00006000)
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#define MODEMR_BOOT_PLL_SHIFT U(13)
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/* Memory mapped Generic timer interfaces */
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#define ARM_SYS_CNTCTL_BASE RCAR_CNTC_BASE
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/* MODEMR PLL masks and bitfield values */
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#define CHECK_MD13_MD14 U(0x6000)
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#define MD14_MD13_TYPE_0 U(0x0000) /* MD14=0 MD13=0 */
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#define MD14_MD13_TYPE_1 U(0x2000) /* MD14=0 MD13=1 */
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#define MD14_MD13_TYPE_2 U(0x4000) /* MD14=1 MD13=0 */
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#define MD14_MD13_TYPE_3 U(0x6000) /* MD14=1 MD13=1 */
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/* Frequency of EXTAL(Hz) */
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#define EXTAL_MD14_MD13_TYPE_0 U(8333300) /* MD14=0 MD13=0 */
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#define EXTAL_MD14_MD13_TYPE_1 U(10000000) /* MD14=0 MD13=1 */
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#define EXTAL_MD14_MD13_TYPE_2 U(12500000) /* MD14=1 MD13=0 */
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#define EXTAL_MD14_MD13_TYPE_3 U(16666600) /* MD14=1 MD13=1 */
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#define EXTAL_SALVATOR_XS U(8320000) /* Salvator-XS */
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#define EXTAL_EBISU U(24000000) /* Ebisu */
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/* CPG write protect registers */
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#define CPGWPR_PASSWORD (0x5A5AFFFFU)
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#define CPGWPCR_PASSWORD (0xA5A50000U)
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/* CA5x Debug Resource control registers */
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#define CPG_CA57DBGRCR (CPG_BASE + 0x2180U)
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#define CPG_CA53DBGRCR (CPG_BASE + 0x1180U)
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#define DBGCPUPREN ((uint32_t)1U << 19U)
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#define CPG_PLL0CR (CPG_BASE + 0x00D8U)
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#define CPG_PLL2CR (CPG_BASE + 0x002CU)
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#define CPG_PLL4CR (CPG_BASE + 0x01F4U)
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/* RST Registers */
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#define RST_BASE (0xE6160000U)
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#define RST_WDTRSTCR (RST_BASE + 0x0054U)
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#define WDTRSTCR_PASSWORD (0xA55A0000U)
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#define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U)
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/* MFIS Registers */
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#define MFISWPCNTR_PASSWORD (0xACCE0000U)
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#define MFISWPCNTR (0xE6260900U)
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/* IPMMU registers */
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#define IPMMU_MM_BASE (0xE67B0000U)
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#define IPMMUMM_IMSCTLR (IPMMU_MM_BASE + 0x0500U)
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#define IPMMUMM_IMAUXCTLR (IPMMU_MM_BASE + 0x0504U)
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#define IPMMUMM_IMSCTLR_ENABLE (0xC0000000U)
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#define IPMMUMM_IMAUXCTLR_NMERGE40_BIT (0x01000000U)
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#define IMSCTLR_DISCACHE (0xE0000000U)
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2018-12-31 15:48:04 +00:00
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#define IPMMU_VP0_BASE (0xFE990000U)
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#define IPMMUVP0_IMSCTLR (IPMMU_VP0_BASE + 0x0500U)
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#define IPMMU_VI0_BASE (0xFEBD0000U)
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#define IPMMUVI0_IMSCTLR (IPMMU_VI0_BASE + 0x0500U)
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#define IPMMU_VI1_BASE (0xFEBE0000U)
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#define IPMMUVI1_IMSCTLR (IPMMU_VI1_BASE + 0x0500U)
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#define IPMMU_PV0_BASE (0xFD800000U)
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#define IPMMUPV0_IMSCTLR (IPMMU_PV0_BASE + 0x0500U)
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#define IPMMU_PV1_BASE (0xFD950000U)
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#define IPMMUPV1_IMSCTLR (IPMMU_PV1_BASE + 0x0500U)
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#define IPMMU_PV2_BASE (0xFD960000U)
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#define IPMMUPV2_IMSCTLR (IPMMU_PV2_BASE + 0x0500U)
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#define IPMMU_PV3_BASE (0xFD970000U)
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#define IPMMUPV3_IMSCTLR (IPMMU_PV3_BASE + 0x0500U)
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#define IPMMU_HC_BASE (0xE6570000U)
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#define IPMMUHC_IMSCTLR (IPMMU_HC_BASE + 0x0500U)
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#define IPMMU_RT_BASE (0xFFC80000U)
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#define IPMMURT_IMSCTLR (IPMMU_RT_BASE + 0x0500U)
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#define IPMMU_MP_BASE (0xEC670000U)
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#define IPMMUMP_IMSCTLR (IPMMU_MP_BASE + 0x0500U)
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#define IPMMU_DS0_BASE (0xE6740000U)
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#define IPMMUDS0_IMSCTLR (IPMMU_DS0_BASE + 0x0500U)
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#define IPMMU_DS1_BASE (0xE7740000U)
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#define IPMMUDS1_IMSCTLR (IPMMU_DS1_BASE + 0x0500U)
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/* ARMREG registers */
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#define P_ARMREG_SEC_CTRL (0xE62711F0U)
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#define P_ARMREG_SEC_CTRL_PROT (0x00000001U)
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/* MIDR */
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#define MIDR_CA57 (0x0D07U << MIDR_PN_SHIFT)
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#define MIDR_CA53 (0x0D03U << MIDR_PN_SHIFT)
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/* for SuspendToRAM */
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#define GPIO_BASE (0xE6050000U)
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#define GPIO_INDT1 (GPIO_BASE + 0x100CU)
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#define GPIO_INDT6 (GPIO_BASE + 0x540CU)
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#define RCAR_COLD_BOOT (0x00U)
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#define RCAR_WARM_BOOT (0x01U)
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#if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
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#define KEEP10_MAGIC (0x55U)
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#endif
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/* lossy registers */
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#define LOSSY_PARAMS_BASE (0x47FD7000U)
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#define AXI_DCMPAREACRA0 (0xE6784100U)
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#define AXI_DCMPAREACRB0 (0xE6784104U)
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#define LOSSY_ENABLE (0x80000000U)
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#define LOSSY_DISABLE (0x00000000U)
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#define LOSSY_FMT_YUVPLANAR (0x00000000U)
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#define LOSSY_FMT_YUV422INTLV (0x20000000U)
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#define LOSSY_FMT_ARGB8888 (0x40000000U)
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#define LOSSY_ST_ADDR0 (0x54000000U)
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#define LOSSY_END_ADDR0 (0x57000000U)
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#define LOSSY_FMT0 LOSSY_FMT_YUVPLANAR
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#define LOSSY_ENA_DIS0 LOSSY_ENABLE
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#define LOSSY_ST_ADDR1 0x0U
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#define LOSSY_END_ADDR1 0x0U
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#define LOSSY_FMT1 LOSSY_FMT_ARGB8888
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#define LOSSY_ENA_DIS1 LOSSY_DISABLE
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#define LOSSY_ST_ADDR2 0x0U
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#define LOSSY_END_ADDR2 0x0U
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#define LOSSY_FMT2 LOSSY_FMT_YUV422INTLV
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#define LOSSY_ENA_DIS2 LOSSY_DISABLE
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2018-11-08 10:20:19 +00:00
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#endif /* RCAR_DEF_H */
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