2016-11-10 16:17:51 +00:00
|
|
|
/*
|
2017-06-05 22:54:46 +01:00
|
|
|
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
|
2016-11-10 16:17:51 +00:00
|
|
|
*
|
2017-05-03 09:38:09 +01:00
|
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
2016-11-10 16:17:51 +00:00
|
|
|
*/
|
|
|
|
|
2018-11-08 10:20:19 +00:00
|
|
|
#ifndef CORTEX_A53_H
|
|
|
|
#define CORTEX_A53_H
|
2016-11-10 16:17:51 +00:00
|
|
|
|
|
|
|
/* Cortex-A53 midr for revision 0 */
|
|
|
|
#define CORTEX_A53_MIDR 0x410FD030
|
|
|
|
|
|
|
|
/* Retention timer tick definitions */
|
|
|
|
#define RETENTION_ENTRY_TICKS_2 0x1
|
|
|
|
#define RETENTION_ENTRY_TICKS_8 0x2
|
|
|
|
#define RETENTION_ENTRY_TICKS_32 0x3
|
|
|
|
#define RETENTION_ENTRY_TICKS_64 0x4
|
|
|
|
#define RETENTION_ENTRY_TICKS_128 0x5
|
|
|
|
#define RETENTION_ENTRY_TICKS_256 0x6
|
|
|
|
#define RETENTION_ENTRY_TICKS_512 0x7
|
|
|
|
|
|
|
|
/*******************************************************************************
|
|
|
|
* CPU Extended Control register specific definitions.
|
|
|
|
******************************************************************************/
|
2017-06-05 22:54:46 +01:00
|
|
|
#define CORTEX_A53_ECTLR p15, 1, c15
|
2016-11-10 16:17:51 +00:00
|
|
|
|
2017-06-05 22:54:46 +01:00
|
|
|
#define CORTEX_A53_ECTLR_SMP_BIT (1 << 6)
|
2016-11-10 16:17:51 +00:00
|
|
|
|
2017-06-05 22:54:46 +01:00
|
|
|
#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT 0
|
|
|
|
#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
|
2016-11-10 16:17:51 +00:00
|
|
|
|
2017-06-05 22:54:46 +01:00
|
|
|
#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT 3
|
|
|
|
#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
|
2016-11-10 16:17:51 +00:00
|
|
|
|
|
|
|
/*******************************************************************************
|
|
|
|
* CPU Memory Error Syndrome register specific definitions.
|
|
|
|
******************************************************************************/
|
2017-06-05 22:54:46 +01:00
|
|
|
#define CORTEX_A53_MERRSR p15, 2, c15
|
2016-11-10 16:17:51 +00:00
|
|
|
|
|
|
|
/*******************************************************************************
|
|
|
|
* CPU Auxiliary Control register specific definitions.
|
|
|
|
******************************************************************************/
|
2017-08-09 16:42:40 +01:00
|
|
|
#define CORTEX_A53_CPUACTLR p15, 0, c15
|
2016-11-10 16:17:51 +00:00
|
|
|
|
2017-08-09 16:42:40 +01:00
|
|
|
#define CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT 44
|
|
|
|
#define CORTEX_A53_CPUACTLR_ENDCCASCI (1 << CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT)
|
|
|
|
#define CORTEX_A53_CPUACTLR_DTAH (1 << 24)
|
2016-11-10 16:17:51 +00:00
|
|
|
|
|
|
|
/*******************************************************************************
|
|
|
|
* L2 Auxiliary Control register specific definitions.
|
|
|
|
******************************************************************************/
|
2017-06-05 22:54:46 +01:00
|
|
|
#define CORTEX_A53_L2ACTLR p15, 1, c15, c0, 0
|
2016-11-10 16:17:51 +00:00
|
|
|
|
2017-06-05 22:54:46 +01:00
|
|
|
#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14)
|
|
|
|
#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3)
|
2016-11-10 16:17:51 +00:00
|
|
|
|
|
|
|
/*******************************************************************************
|
|
|
|
* L2 Extended Control register specific definitions.
|
|
|
|
******************************************************************************/
|
2017-06-05 22:54:46 +01:00
|
|
|
#define CORTEX_A53_L2ECTLR p15, 1, c9, c0, 3
|
2016-11-10 16:17:51 +00:00
|
|
|
|
2017-06-05 22:54:46 +01:00
|
|
|
#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT 0
|
|
|
|
#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT)
|
2016-11-10 16:17:51 +00:00
|
|
|
|
|
|
|
/*******************************************************************************
|
|
|
|
* L2 Memory Error Syndrome register specific definitions.
|
|
|
|
******************************************************************************/
|
2017-06-05 22:54:46 +01:00
|
|
|
#define CORTEX_A53_L2MERRSR p15, 3, c15
|
2016-11-10 16:17:51 +00:00
|
|
|
|
2018-11-08 10:20:19 +00:00
|
|
|
#endif /* CORTEX_A53_H */
|