2017-06-28 09:11:31 +01:00
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <console.h>
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#include <debug.h>
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2018-01-02 16:53:08 +00:00
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#include <dw_mmc.h>
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#include <emmc.h>
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2017-06-28 09:11:31 +01:00
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#include <errno.h>
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#include <generic_delay_timer.h>
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#include <mmio.h>
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#include <partition/partition.h>
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#include <platform.h>
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#include <string.h>
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#include "hi3798cv200.h"
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#include "plat_private.h"
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/* Memory ranges for code and read only data sections */
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#define BL2_RO_BASE (unsigned long)(&__RO_START__)
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#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
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/* Memory ranges for coherent memory section */
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#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
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#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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typedef struct bl2_to_bl31_params_mem {
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bl31_params_t bl31_params;
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image_info_t bl31_image_info;
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2017-10-27 17:59:41 +01:00
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image_info_t bl32_image_info;
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2017-06-28 09:11:31 +01:00
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image_info_t bl33_image_info;
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entry_point_info_t bl33_ep_info;
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2017-10-27 17:59:41 +01:00
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entry_point_info_t bl32_ep_info;
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2017-06-28 09:11:31 +01:00
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entry_point_info_t bl31_ep_info;
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} bl2_to_bl31_params_mem_t;
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static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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static bl2_to_bl31_params_mem_t bl31_params_mem;
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meminfo_t *bl2_plat_sec_mem_layout(void)
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{
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return &bl2_tzram_layout;
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}
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bl31_params_t *bl2_plat_get_bl31_params(void)
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{
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bl31_params_t *bl2_to_bl31_params = NULL;
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/*
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* Initialise the memory for all the arguments that needs to
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* be passed to BL3-1
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*/
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memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t));
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/* Assign memory for TF related information */
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bl2_to_bl31_params = &bl31_params_mem.bl31_params;
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SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
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/* Fill BL3-1 related information */
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bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info,
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PARAM_IMAGE_BINARY, VERSION_1, 0);
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2017-10-27 17:59:41 +01:00
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/* Fill BL3-2 related information if it exists */
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#ifdef BL32_BASE
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bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
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VERSION_1, 0);
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bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
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VERSION_1, 0);
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#endif
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2017-06-28 09:11:31 +01:00
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/* Fill BL3-3 related information */
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bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
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PARAM_EP, VERSION_1, 0);
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/* BL3-3 expects to receive the primary CPU MPID (through x0) */
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bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
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bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info,
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PARAM_IMAGE_BINARY, VERSION_1, 0);
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return bl2_to_bl31_params;
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}
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struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
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{
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return &bl31_params_mem.bl31_ep_info;
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}
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void bl2_plat_set_bl31_ep_info(image_info_t *image,
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entry_point_info_t *bl31_ep_info)
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{
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SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
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bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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}
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2017-10-27 17:59:41 +01:00
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/*******************************************************************************
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* Before calling this function BL32 is loaded in memory and its entrypoint
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* is set by load_image. This is a placeholder for the platform to change
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* the entrypoint of BL32 and set SPSR and security state.
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* On Poplar we only set the security state of the entrypoint
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******************************************************************************/
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#ifdef BL32_BASE
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void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
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entry_point_info_t *bl32_ep_info)
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{
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SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
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/*
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* The Secure Payload Dispatcher service is responsible for
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* setting the SPSR prior to entry into the BL32 image.
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*/
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bl32_ep_info->spsr = 0;
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}
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/*******************************************************************************
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* Populate the extents of memory available for loading BL32
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******************************************************************************/
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void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
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{
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/*
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* Populate the extents of memory available for loading BL32.
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*/
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bl32_meminfo->total_base = BL32_BASE;
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bl32_meminfo->free_base = BL32_BASE;
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bl32_meminfo->total_size =
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(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
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bl32_meminfo->free_size =
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(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
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}
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#endif /* BL32_BASE */
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2017-06-28 09:11:31 +01:00
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static uint32_t hisi_get_spsr_for_bl33_entry(void)
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{
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unsigned long el_status;
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unsigned int mode;
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uint32_t spsr;
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/* Figure out what mode we enter the non-secure world in */
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el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
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el_status &= ID_AA64PFR0_ELX_MASK;
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mode = (el_status) ? MODE_EL2 : MODE_EL1;
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/*
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* TODO: Consider the possibility of specifying the SPSR in
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* the FIP ToC and allowing the platform to have a say as
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* well.
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*/
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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void bl2_plat_set_bl33_ep_info(image_info_t *image,
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entry_point_info_t *bl33_ep_info)
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{
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SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
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bl33_ep_info->spsr = hisi_get_spsr_for_bl33_entry();
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bl33_ep_info->args.arg2 = image->image_size;
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}
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void bl2_plat_flush_bl31_params(void)
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{
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flush_dcache_range((unsigned long)&bl31_params_mem,
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sizeof(bl2_to_bl31_params_mem_t));
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}
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void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
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{
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bl33_meminfo->total_base = DDR_BASE;
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bl33_meminfo->total_size = DDR_SIZE;
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bl33_meminfo->free_base = DDR_BASE;
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bl33_meminfo->free_size = DDR_SIZE;
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}
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void bl2_early_platform_setup(meminfo_t *mem_layout)
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{
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2018-01-15 15:29:47 +00:00
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#if !POPLAR_RECOVERY
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2018-01-02 16:53:08 +00:00
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dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE);
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2018-01-15 15:29:47 +00:00
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#endif
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2018-01-02 16:53:08 +00:00
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2017-06-28 09:11:31 +01:00
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console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
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/* Enable arch timer */
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generic_delay_timer_init();
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bl2_tzram_layout = *mem_layout;
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2018-01-02 16:53:08 +00:00
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2018-01-15 15:29:47 +00:00
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#if !POPLAR_RECOVERY
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2018-01-02 16:53:08 +00:00
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/* SoC-specific emmc register are initialized/configured by bootrom */
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INFO("BL2: initializing emmc\n");
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dw_mmc_init(¶ms);
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2018-01-15 15:29:47 +00:00
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#endif
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2018-01-02 16:53:08 +00:00
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plat_io_setup();
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2017-06-28 09:11:31 +01:00
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}
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void bl2_plat_arch_setup(void)
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{
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plat_configure_mmu_el1(bl2_tzram_layout.total_base,
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bl2_tzram_layout.total_size,
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BL2_RO_BASE,
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BL2_RO_LIMIT,
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BL2_COHERENT_RAM_BASE,
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BL2_COHERENT_RAM_LIMIT);
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}
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void bl2_platform_setup(void)
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{
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}
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unsigned long plat_get_ns_image_entrypoint(void)
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{
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2017-10-26 16:09:14 +01:00
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return PLAT_POPLAR_NS_IMAGE_OFFSET;
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2017-06-28 09:11:31 +01:00
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}
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