2016-10-14 02:13:34 +01:00
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#
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# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# We don't use BL1 or BL2, so BL31 is the first image to execute
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RESET_TO_BL31 := 1
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# Only one core starts up at first
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COLD_BOOT_SINGLE_CPU := 1
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# We can choose where a core starts executing
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PROGRAMMABLE_RESET_ADDRESS:= 1
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# System coherency is managed in hardware
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HW_ASSISTED_COHERENCY := 1
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USE_COHERENT_MEM := 0
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ERROR_DEPRECATED := 1
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ENABLE_PLAT_COMPAT := 0
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# A53 erratum for SoC. (enable them all)
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ERRATA_A53_826319 := 1
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ERRATA_A53_835769 := 1
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ERRATA_A53_836870 := 1
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ERRATA_A53_843419 := 1
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ERRATA_A53_855873 := 1
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PLAT_INCLUDES += \
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-I${PLAT_PATH}/include \
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-Iinclude/plat/arm/common/ \
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-Iinclude/plat/arm/common/aarch64/ \
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PLAT_BL_COMMON_SOURCES += \
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lib/cpus/aarch64/cortex_a53.S \
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BL31_SOURCES += \
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${PLAT_PATH}/common/k3_bl31_setup.c \
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2016-10-18 20:32:06 +01:00
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${PLAT_PATH}/common/k3_helpers.S \
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